Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1cb804b9 authored by Mark A. Greer's avatar Mark A. Greer Committed by Paul Walmsley
Browse files

ARM: AM33XX: hwmod: Update and uncomment AES0 module data 



Update the AES0 HIB2 module's hwmod data for the am33xx SoC.
Also, remove it from the '#if 0' block that its currently
inside so the data is actually available for use.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarMark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: fixed lines causing sparse warnings]
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent ff2acd7d

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

+42 −9
Original line number Original line Diff line number Diff line
@@ -417,7 +417,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { 
 *    - clkdiv32k

 *    - clkdiv32k

 *    - debugss

 *    - debugss

 *    - ocp watch point

 *    - ocp watch point

 *    - aes0

 */

 */

#if 0

#if 0

/*

/*
@@ -498,25 +497,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { 
		},

		},

	},

	},

};

};

#endif





/*

/*

 * 'aes' class

 * 'aes0' class

 */

 */

static struct omap_hwmod_class am33xx_aes_hwmod_class = {

static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {

	.name		= "aes",

	.rev_offs	= 0x80,

	.sysc_offs	= 0x84,

	.syss_offs	= 0x88,

	.sysc_flags	= SYSS_HAS_RESET_STATUS,

};



static struct omap_hwmod_class am33xx_aes0_hwmod_class = {

	.name		= "aes0",

	.sysc		= &am33xx_aes0_sysc,

};

};





static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {

static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {

	{ .irq = 102 + OMAP_INTC_START, },

	{ .irq = 103 + OMAP_INTC_START, },

	{ .irq = -1 },

	{ .irq = -1 },

};

};





static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {

	{ .name = "tx", .dma_req = 6, },

	{ .name = "rx", .dma_req = 5, },

	{ .dma_req = -1 }

};



static struct omap_hwmod am33xx_aes0_hwmod = {

static struct omap_hwmod am33xx_aes0_hwmod = {

	.name		= "aes0",

	.name		= "aes",

	.class		= &am33xx_aes_hwmod_class,

	.class		= &am33xx_aes0_hwmod_class,

	.clkdm_name	= "l3_clkdm",

	.clkdm_name	= "l3_clkdm",

	.mpu_irqs	= am33xx_aes0_irqs,

	.mpu_irqs	= am33xx_aes0_irqs,

	.main_clk	= "l3_gclk",

	.sdma_reqs	= am33xx_aes0_edma_reqs,

	.main_clk	= "aes0_fck",

	.prcm		= {

	.prcm		= {

		.omap4	= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,

			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -524,7 +539,6 @@ static struct omap_hwmod am33xx_aes0_hwmod = { 
		},

		},

	},

	},

};

};

#endif





/* sha0 HIB2 (the 'P' (public) device) */

/* sha0 HIB2 (the 'P' (public) device) */

static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {

static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
@@ -3464,6 +3478,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};

};





/* l3 main -> AES0 HIB2 */

static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {

	{

		.pa_start	= 0x53500000,

		.pa_end		= 0x53500000 + SZ_1M - 1,

		.flags		= ADDR_TYPE_RT

	},

	{ }

};



static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {

	.master		= &am33xx_l3_main_hwmod,

	.slave		= &am33xx_aes0_hwmod,

	.clk		= "aes0_fck",

	.addr		= am33xx_aes0_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {

static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {

	&am33xx_l4_fw__emif_fw,

	&am33xx_l4_fw__emif_fw,

	&am33xx_l3_main__emif,

	&am33xx_l3_main__emif,
@@ -3545,6 +3577,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 
	&am33xx_l4_hs__cpgmac0,

	&am33xx_l4_hs__cpgmac0,

	&am33xx_cpgmac0__mdio,

	&am33xx_cpgmac0__mdio,

	&am33xx_l3_main__sha0,

	&am33xx_l3_main__sha0,

	&am33xx_l3_main__aes0,

	NULL,

	NULL,

};

};