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Commit 1c90e170 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-soc-4.9' of... 

Merge tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Pull "i.MX SoC updates for 4.9" from Shawn Guo:

 - Set INT_MEM_CLK_LPM bit to get proper WAIT mode support on i.MX6SX.
   This is a workaround for i.MX6SX WAIT mode hardware issue.
 - Enable cpuidle support with 3 low-power states (WFI, WAIT, POWER-OFF)
   for i.MX6UL.

* tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: build cpuidle-imx6sx.o for imx6ul
  ARM: imx: add cpuidle support for i.mx6ul
  ARM: imx: enable WAIT mode hardware workaround for imx6sx
  ARM: imx: rename imx6q_set_int_mem_clk_lpm() function
parents 4a5c9946 d64299da

arch/arm/mach-imx/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o 
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o

obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o

endif



ifdef CONFIG_SND_IMX_SOC

arch/arm/mach-imx/common.h

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ void imx_anatop_init(void); 
void imx_anatop_pre_suspend(void);

void imx_anatop_post_resume(void);

int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);

void imx6q_set_int_mem_clk_lpm(bool enable);

void imx6_set_int_mem_clk_lpm(bool enable);

void imx6sl_set_wait_clk(bool enter);

int imx_mmdc_get_ddr_type(void);

arch/arm/mach-imx/cpuidle-imx6q.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused); 
int __init imx6q_cpuidle_init(void)

{

	/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */

	imx6q_set_int_mem_clk_lpm(true);

	imx6_set_int_mem_clk_lpm(true);



	return cpuidle_register(&imx6q_cpuidle_driver, NULL);

}

arch/arm/mach-imx/cpuidle-imx6sx.c

+11 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/module.h>

#include <asm/cacheflush.h>

#include <asm/cpuidle.h>

#include <asm/suspend.h>
@@ -17,6 +18,15 @@ 


static int imx6sx_idle_finish(unsigned long val)

{

	/*

	 * for Cortex-A7 which has an internal L2

	 * cache, need to flush it before powering

	 * down ARM platform, since flushing L1 cache

	 * here again has very small overhead, compared

	 * to adding conditional code for L2 cache type,

	 * just call flush_cache_all() is fine.

	 */

	flush_cache_all();

	cpu_do_idle();



	return 0;
@@ -90,6 +100,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { 


int __init imx6sx_cpuidle_init(void)

{

	imx6_set_int_mem_clk_lpm(true);

	imx6_enable_rbc(false);

	/*

	 * set ARM power up/down timing to the fastest,

arch/arm/mach-imx/mach-imx6ul.c

+3 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <asm/mach/map.h>



#include "common.h"

#include "cpuidle.h"



static void __init imx6ul_enet_clk_init(void)

{
@@ -79,6 +80,8 @@ static void __init imx6ul_init_irq(void) 


static void __init imx6ul_init_late(void)

{

	imx6sx_cpuidle_init();



	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))

		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);

}