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Commit 1c431cb4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next 

- Vast improvements to gk20a instmem handling.
- Improved PGOB detection + GK107 support.
- Compatibility between old/new interfaces added, final missing piece to
finally enabling userspace to start using them.
- Kepler GDDR5 PLL stability improvements
- Support for non-GPIO (PWM) voltage controllers
- G8x/GT2xx memory clock improvements
- Misc other fixes

* 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (45 commits)
  drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interop
  drm/nouveau/abi16: implement limited interoperability with usif/nvif
  drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()
  drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()
  drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
  drm/nouveau/pci: enable c800 magic for Lenovo Y510P
  drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
  drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200
  drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristic
  drm/nouveau/fb/ramnv50: Script changes for G94 and up
  drm/nouveau/fb/ramnv50: Deal with cards without timing entries
  drm/nouveau/fb/ramnv50: Voltage GPIOs
  drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2
  drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for it
  drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to generic
  drm/nouveau/bios/rammap: Identify DLLoff for >= GF100
  drm/nouveau/pci: Handle 5-bit and 8-bit tag field
  drm/nouveau/disp,pm: constify nvkm_object_func structures
  drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+
  drm/nouveau/gr: document mp error 0x10
  ...
parents b4590047 79ef5dca

drivers/gpu/drm/nouveau/include/nvif/os.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <linux/agp_backend.h>

#include <linux/reset.h>

#include <linux/iommu.h>

#include <linux/of_device.h>



#include <asm/unaligned.h>

drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h

+12 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <core/mm.h>



struct nvkm_device_tegra {

	const struct nvkm_device_tegra_func *func;

	struct nvkm_device device;

	struct platform_device *pdev;

	int irq;
@@ -28,7 +29,17 @@ struct nvkm_device_tegra { 
	int gpu_speedo;

};



int nvkm_device_tegra_new(struct platform_device *,

struct nvkm_device_tegra_func {

	/*

	 * If an IOMMU is used, indicates which address bit will trigger a

	 * IOMMU translation when set (when this bit is not set, IOMMU is

	 * bypassed). A value of 0 means an IOMMU is never used.

	 */

	u8 iommu_bit;

};



int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,

			  struct platform_device *,

			  const char *cfg, const char *dbg,

			  bool detect, bool mmio, u64 subdev_mask,

			  struct nvkm_device **);

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ enum dcb_gpio_func_name { 
	DCB_GPIO_VID5 = 0x74,

	DCB_GPIO_VID6 = 0x75,

	DCB_GPIO_VID7 = 0x76,

	DCB_GPIO_VID_PWM = 0x81,

};



#define DCB_GPIO_LOG_DIR     0x02

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h

+0 −2
Original line number Diff line number Diff line
@@ -4,8 +4,6 @@ struct nvbios_pmuT { 
};



u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);

u32 nvbios_pmuTp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,

		 struct nvbios_pmuT *);



struct nvbios_pmuE {

	u8  type;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h

+1 −1
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct nvbios_ramcfg { 
	unsigned ramcfg_timing;

	unsigned ramcfg_DLLoff;

	unsigned ramcfg_RON;

	unsigned ramcfg_FBVDDQ;

	union {

		struct {

			unsigned ramcfg_00_03_01:1;
@@ -78,7 +79,6 @@ struct nvbios_ramcfg { 
			unsigned ramcfg_11_01_04:1;

			unsigned ramcfg_11_01_08:1;

			unsigned ramcfg_11_01_10:1;

			unsigned ramcfg_11_01_20:1;

			unsigned ramcfg_11_01_40:1;

			unsigned ramcfg_11_01_80:1;

			unsigned ramcfg_11_02_03:2;