Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1bd40543 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2015-09-01

This series contains updates to i40e, ixgbe and ixgbevf.

Anjali fixes a bug in i40e where the port is not receiving multicast or VLAN
tagged packets in promiscuous mode.  Which can occur when a software bridge
is created on top of the device.

Don adds support in ixgbe that indicates the presence of management firmware.
Added support for entering low power link up state on devices that support
it when the device is closing or suspending.  Updated the driver to report
unknown bus speed and width since IOSF does not report a PCIe bus speed or
width for X550 devices.  Also added the new bus type for integrated I/O
interface (IOSF).  Cleaned up of redundant code in ixgbe.

Mark adds support for UDP-encapsulation transmit checksum and for VXLAN
receive offloads.  Introduces a helper function to do the register access
and processing to avoid needless PHY access on copper PHYs.  Added support
for reporting 2.5G link speed.  Fixed warnings resulting from redundant
initializations of the get_bus_info field.

Maninder Singh updates the ixgbe driver to use kzalloc instead of kcalloc
for allocation of one thing.

Tom Barbette adds support for ethtool to change the rxfh indirection table
and/or key using ethtool interface.

Emil resolves an issue where users were not able to dynamically set number
of queues for 82598 via ethtool -L.

Alex Williamson removes bimodal SR-IOV disabling behavior since it is
confusing to users and results in a state where the PF is broken for other
uses unless the user sets sriov_numvfs to zero prior to unbinding the
device.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a17ace95 990a2d6e

drivers/net/ethernet/intel/i40e/i40e.h

+1 −0
Original line number Diff line number Diff line
@@ -372,6 +372,7 @@ struct i40e_pf { 
#ifdef CONFIG_DEBUG_FS

	struct dentry *i40e_dbg_pf;

#endif /* CONFIG_DEBUG_FS */

	bool cur_promisc;



	u16 instance; /* A unique number per i40e_pf instance in the system */

drivers/net/ethernet/intel/i40e/i40e_main.c

+29 −8
Original line number Diff line number Diff line
@@ -1937,15 +1937,35 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi) 
		cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||

			       test_bit(__I40E_FILTER_OVERFLOW_PROMISC,

					&vsi->state));

		ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,

		if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {

			/* set defport ON for Main VSI instead of true promisc

			 * this way we will get all unicast/multicast and VLAN

			 * promisc behavior but will not get VF or VMDq traffic

			 * replicated on the Main VSI.

			 */

			if (pf->cur_promisc != cur_promisc) {

				pf->cur_promisc = cur_promisc;

				i40e_do_reset_safe(pf,

						BIT(__I40E_PF_RESET_REQUESTED));

			}

		} else {

			ret = i40e_aq_set_vsi_unicast_promiscuous(

							  &vsi->back->hw,

							  vsi->seid,

							  cur_promisc, NULL);

			if (ret)

				dev_info(&pf->pdev->dev,

				 "set uni promisc failed, err %s, aq_err %s\n",

				 i40e_stat_str(&pf->hw, ret),

				 i40e_aq_str(&pf->hw,

					     pf->hw.aq.asq_last_status));

					 "set unicast promisc failed, err %d, aq_err %d\n",

					 ret, pf->hw.aq.asq_last_status);

			ret = i40e_aq_set_vsi_multicast_promiscuous(

							  &vsi->back->hw,

							  vsi->seid,

							  cur_promisc, NULL);

			if (ret)

				dev_info(&pf->pdev->dev,

					 "set multicast promisc failed, err %d, aq_err %d\n",

					 ret, pf->hw.aq.asq_last_status);

		}

		ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,

						vsi->seid,

						cur_promisc, NULL);
@@ -4001,6 +4021,7 @@ static void i40e_vsi_close(struct i40e_vsi *vsi) 
	i40e_vsi_free_irq(vsi);

	i40e_vsi_free_tx_resources(vsi);

	i40e_vsi_free_rx_resources(vsi);

	vsi->current_netdev_flags = 0;

}



/**
@@ -9312,7 +9333,7 @@ void i40e_veb_release(struct i40e_veb *veb) 
static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)

{

	struct i40e_pf *pf = veb->pf;

	bool is_default = false;

	bool is_default = veb->pf->cur_promisc;

	bool is_cloud = false;

	int ret;

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+7 −0
Original line number Diff line number Diff line
@@ -630,6 +630,7 @@ struct ixgbe_adapter { 
#define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 21)

#define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 22)

#define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 23)

#define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE	BIT(24)



	u32 flags2;

#define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1 << 0)
@@ -644,6 +645,9 @@ struct ixgbe_adapter { 
#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP		(u32)(1 << 9)

#define IXGBE_FLAG2_PTP_PPS_ENABLED		(u32)(1 << 10)

#define IXGBE_FLAG2_PHY_INTERRUPT		(u32)(1 << 11)

#ifdef CONFIG_IXGBE_VXLAN

#define IXGBE_FLAG2_VXLAN_REREG_NEEDED		BIT(12)

#endif



	/* Tx fast path data */

	int num_tx_queues;
@@ -757,7 +761,9 @@ struct ixgbe_adapter { 
	u32 timer_event_accumulator;

	u32 vferr_refcount;

	struct ixgbe_mac_addr *mac_table;

#ifdef CONFIG_IXGBE_VXLAN

	u16 vxlan_port;

#endif

	struct kobject *info_kobj;

#ifdef CONFIG_IXGBE_HWMON

	struct hwmon_buff *ixgbe_hwmon_buff;
@@ -967,4 +973,5 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 
				  struct ixgbe_adapter *adapter,

				  struct ixgbe_ring *tx_ring);

u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);

void ixgbe_store_reta(struct ixgbe_adapter *adapter);

#endif /* _IXGBE_H_ */

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+55 −34
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel 10 Gigabit PCI Express Linux driver

  Copyright(c) 1999 - 2014 Intel Corporation.

  Copyright(c) 1999 - 2015 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,
@@ -504,16 +504,12 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 
 **/

static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)

{

	u32 autoc2_reg, fwsm;

	u32 autoc2_reg;

	u16 ee_ctrl_2 = 0;



	hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);



	/* Check to see if MNG FW could be enabled */

	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));



	if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&

	    !hw->wol_enabled &&

	if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&

	    ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {

		autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

		autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
@@ -1245,6 +1241,25 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 
	return status;

}



/**

 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete

 * @hw: pointer to hardware structure

 * @fdircmd: current value of FDIRCMD register

 */

static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)

{

	int i;



	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {

		*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);

		if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))

			return 0;

		udelay(10);

	}



	return IXGBE_ERR_FDIR_CMD_INCOMPLETE;

}



/**

 *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.

 *  @hw: pointer to hardware structure
@@ -1253,6 +1268,8 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 
{

	int i;

	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);

	u32 fdircmd;

	s32 err;



	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
@@ -1260,15 +1277,10 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 
	 * Before starting reinitialization process,

	 * FDIRCMD.CMD must be zero.

	 */

	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {

		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &

		      IXGBE_FDIRCMD_CMD_MASK))

			break;

		udelay(10);

	}

	if (i >= IXGBE_FDIRCMD_CMD_POLL) {

		hw_dbg(hw, "Flow Director previous command isn't complete, aborting table re-initialization.\n");

		return IXGBE_ERR_FDIR_REINIT_FAILED;

	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);

	if (err) {

		hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n");

		return err;

	}



	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
@@ -1507,6 +1519,9 @@ static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 
 *  @input: unique input dword

 *  @common: compressed common input dword

 *  @queue: queue index to direct traffic to

 *

 * Note that the tunnel bit in input must not be set when the hardware

 * tunneling support does not exist.

 **/

s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,

					  union ixgbe_atr_hash_dword input,
@@ -1514,13 +1529,18 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 
					  u8 queue)

{

	u64 fdirhashcmd;

	u8 flow_type;

	bool tunnel;

	u32 fdircmd;



	/*

	 * Get the flow_type in order to program FDIRCMD properly

	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6

	 */

	switch (input.formatted.flow_type) {

	tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);

	flow_type = input.formatted.flow_type &

		    (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);

	switch (flow_type) {

	case IXGBE_ATR_FLOW_TYPE_TCPV4:

	case IXGBE_ATR_FLOW_TYPE_UDPV4:

	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
@@ -1536,8 +1556,10 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 
	/* configure FDIRCMD register */

	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |

		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;

	fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;

	fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;

	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;

	if (tunnel)

		fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;



	/*

	 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
@@ -1758,6 +1780,7 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 
					  u16 soft_id, u8 queue)

{

	u32 fdirport, fdirvlan, fdirhash, fdircmd;

	s32 err;



	/* currently IPv6 is not supported, must be programmed with 0 */

	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
@@ -1806,6 +1829,11 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 
	fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;



	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);

	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);

	if (err) {

		hw_dbg(hw, "Flow Director command did not complete!\n");

		return err;

	}



	return 0;

}
@@ -1815,9 +1843,8 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 
					  u16 soft_id)

{

	u32 fdirhash;

	u32 fdircmd = 0;

	u32 retry_count;

	s32 err = 0;

	u32 fdircmd;

	s32 err;



	/* configure FDIRHASH register */

	fdirhash = input->formatted.bkt_hash;
@@ -1830,18 +1857,12 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 
	/* Query if filter is present */

	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);



	for (retry_count = 10; retry_count; retry_count--) {

		/* allow 10us for query to process */

		udelay(10);

		/* verify query completed successfully */

		fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);

		if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))

			break;

	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);

	if (err) {

		hw_dbg(hw, "Flow Director command did not complete!\n");

		return err;

	}



	if (!retry_count)

		err = IXGBE_ERR_FDIR_REINIT_FAILED;



	/* if filter exists in hardware then remove it */

	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {

		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
@@ -1850,7 +1871,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 
				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);

	}



	return err;

	return 0;

}



/**

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+15 −0
Original line number Diff line number Diff line
@@ -3905,3 +3905,18 @@ void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 
		}

	}

}



/** ixgbe_mng_present - returns true when management capability is present

 * @hw: pointer to hardware structure

 **/

bool ixgbe_mng_present(struct ixgbe_hw *hw)

{

	u32 fwsm;



	if (hw->mac.type < ixgbe_mac_82599EB)

		return false;



	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));

	fwsm &= IXGBE_FWSM_MODE_MASK;

	return fwsm == IXGBE_FWSM_FW_MODE_PT;

}