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Commit 1b85147b authored by Imre Deak's avatar Imre Deak
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drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout 

On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks
like they happen sometime after a system suspend/resume cycle, with the
same power well enabling succeeding both before and after the failed
one and no other problems observed. The current timeout in the code is
not actually specified by BSpec, so let's try to increase that until a
BSpec update.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771


Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180409122716.4055-1-imre.deak@intel.com


Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent 8b69449d

drivers/gpu/drm/i915/intel_dpio_phy.c

+6 −5
Original line number Diff line number Diff line
@@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
	 * all 1s.  Eventually they become accessible as they power up, then

	 * the reserved bit will give the default 0.  Poll on the reserved bit

	 * becoming 0 to find when the PHY is accessible.

	 * HW team confirmed that the time to reach phypowergood status is

	 * anywhere between 50 us and 100us.

	 * The flag should get set in 100us according to the HW team, but

	 * use 1ms due to occasional timeouts observed with that.

	 */

	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &

		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {

	if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),

				       PHY_RESERVED | PHY_POWER_GOOD,

				       PHY_POWER_GOOD,

				       1))

		DRM_ERROR("timeout during PHY%d power on\n", phy);

	}



	/* Program PLL Rcomp code offset */

	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));