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Commit 1abc4dc7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Parametrize VLV_DDL registers 



The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.

Note that we now fill out the drain latency for pipe C on CHV which we
didn't do before. The rest of the pipe C watermarks are still untouched
but that will be remedied later by adding a proper cherryview_update_wm()
function.

v2: Add a note about CHV pipe C changes (Paulo)

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0a560674

drivers/gpu/drm/i915/i915_reg.h

+13 −41
Original line number Diff line number Diff line
@@ -3999,47 +3999,19 @@ enum punit_power_well { 
/* drain latency register values*/

#define DRAIN_LATENCY_PRECISION_32	32

#define DRAIN_LATENCY_PRECISION_64	64

#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)

#define DDL_CURSORA_PRECISION_64	(1<<31)

#define DDL_CURSORA_PRECISION_32	(0<<31)

#define DDL_CURSORA_SHIFT		24

#define DDL_SPRITEB_PRECISION_64	(1<<23)

#define DDL_SPRITEB_PRECISION_32	(0<<23)

#define DDL_SPRITEB_SHIFT		16

#define DDL_SPRITEA_PRECISION_64	(1<<15)

#define DDL_SPRITEA_PRECISION_32	(0<<15)

#define DDL_SPRITEA_SHIFT		8

#define DDL_PLANEA_PRECISION_64		(1<<7)

#define DDL_PLANEA_PRECISION_32		(0<<7)

#define DDL_PLANEA_SHIFT		0



#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)

#define DDL_CURSORB_PRECISION_64	(1<<31)

#define DDL_CURSORB_PRECISION_32	(0<<31)

#define DDL_CURSORB_SHIFT		24

#define DDL_SPRITED_PRECISION_64	(1<<23)

#define DDL_SPRITED_PRECISION_32	(0<<23)

#define DDL_SPRITED_SHIFT		16

#define DDL_SPRITEC_PRECISION_64	(1<<15)

#define DDL_SPRITEC_PRECISION_32	(0<<15)

#define DDL_SPRITEC_SHIFT		8

#define DDL_PLANEB_PRECISION_64		(1<<7)

#define DDL_PLANEB_PRECISION_32		(0<<7)

#define DDL_PLANEB_SHIFT		0



#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)

#define DDL_CURSORC_PRECISION_64	(1<<31)

#define DDL_CURSORC_PRECISION_32	(0<<31)

#define DDL_CURSORC_SHIFT		24

#define DDL_SPRITEF_PRECISION_64	(1<<23)

#define DDL_SPRITEF_PRECISION_32	(0<<23)

#define DDL_SPRITEF_SHIFT		16

#define DDL_SPRITEE_PRECISION_64	(1<<15)

#define DDL_SPRITEE_PRECISION_32	(0<<15)

#define DDL_SPRITEE_SHIFT		8

#define DDL_PLANEC_PRECISION_64		(1<<7)

#define DDL_PLANEC_PRECISION_32		(0<<7)

#define DDL_PLANEC_SHIFT		0

#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

#define DDL_CURSOR_PRECISION_64		(1<<31)

#define DDL_CURSOR_PRECISION_32		(0<<31)

#define DDL_CURSOR_SHIFT		24

#define DDL_SPRITE1_PRECISION_64	(1<<23)

#define DDL_SPRITE1_PRECISION_32	(0<<23)

#define DDL_SPRITE1_SHIFT		16

#define DDL_SPRITE0_PRECISION_64	(1<<15)

#define DDL_SPRITE0_PRECISION_32	(0<<15)

#define DDL_SPRITE0_SHIFT		8

#define DDL_PLANE_PRECISION_64		(1<<7)

#define DDL_PLANE_PRECISION_32		(0<<7)

#define DDL_PLANE_SHIFT			0



/* FIFO watermark sizes etc */

#define G4X_FIFO_LINE_SIZE	64

drivers/gpu/drm/i915/intel_pm.c

+23 −29
Original line number Diff line number Diff line
@@ -1313,35 +1313,29 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, 
static void vlv_update_drain_latency(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int planea_prec, planea_dl, planeb_prec, planeb_dl;

	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;

	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is

							either 16 or 32 */



	/* For plane A, Cursor A */

	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,

				      &cursor_prec_mult, &cursora_dl)) {

		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;

		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;



		I915_WRITE(VLV_DDL1, cursora_prec |

				(cursora_dl << DDL_CURSORA_SHIFT) |

				planea_prec | planea_dl);

	}



	/* For plane B, Cursor B */

	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,

				      &cursor_prec_mult, &cursorb_dl)) {

		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;

		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?

			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;



		I915_WRITE(VLV_DDL2, cursorb_prec |

				(cursorb_dl << DDL_CURSORB_SHIFT) |

				planeb_prec | planeb_dl);

	enum pipe pipe;



	for_each_pipe(pipe) {

		int plane_prec, plane_dl;

		int cursor_prec, cursor_dl;

		int plane_prec_mult, cursor_prec_mult;



		if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,

					       &cursor_prec_mult, &cursor_dl))

			continue;



		/*

		 * FIXME CHV spec still lists 16 and 32 as the precision

		 * values. Need to figure out if spec is outdated or what.

		 */

		cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?

			DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;

		plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?

			DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;



		I915_WRITE(VLV_DDL(pipe), cursor_prec |

			   (cursor_dl << DDL_CURSOR_SHIFT) |

			   plane_prec | (plane_dl << DDL_PLANE_SHIFT));

	}

}