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Commit 1a8aa8ac authored by Denys Vlasenko's avatar Denys Vlasenko Committed by Ingo Molnar
Browse files

x86/apic: Deinline __default_send_IPI_*, save ~200 bytes 



__default_send_IPI_shortcut: 49 bytes, 2 callsites
__default_send_IPI_dest_field: 108 bytes, 7 callsites

     text     data      bss       dec     hex filename
 96184086 20860488 36122624 153167198 921255e vmlinux_before
 96183823 20860520 36122624 153166967 9212477 vmlinux

Signed-off-by: default avatarDenys Vlasenko <dvlasenk@redhat.com>
Cc: Borislav Petkov <bp@alien.de>
Cc: Daniel J Blueman <daniel@numascale.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mike Travis <travis@sgi.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/1457287876-6001-1-git-send-email-dvlasenk@redhat.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent fe36d891

arch/x86/include/asm/ipi.h

+2 −56
Original line number Diff line number Diff line
@@ -57,67 +57,13 @@ static inline void __xapic_wait_icr_idle(void) 
		cpu_relax();

}



static inline void

__default_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest)

{

	/*

	 * Subtle. In the case of the 'never do double writes' workaround

	 * we have to lock out interrupts to be safe.  As we don't care

	 * of the value read we use an atomic rmw access to avoid costly

	 * cli/sti.  Otherwise we use an even cheaper single atomic write

	 * to the APIC.

	 */

	unsigned int cfg;



	/*

	 * Wait for idle.

	 */

	__xapic_wait_icr_idle();



	/*

	 * No need to touch the target chip field

	 */

	cfg = __prepare_ICR(shortcut, vector, dest);



	/*

	 * Send the IPI. The write to APIC_ICR fires this off.

	 */

	native_apic_mem_write(APIC_ICR, cfg);

}

void __default_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest);



/*

 * This is used to send an IPI with no shorthand notation (the destination is

 * specified in bits 56 to 63 of the ICR).

 */

static inline void

 __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)

{

	unsigned long cfg;



	/*

	 * Wait for idle.

	 */

	if (unlikely(vector == NMI_VECTOR))

		safe_apic_wait_icr_idle();

	else

		__xapic_wait_icr_idle();



	/*

	 * prepare target chip field

	 */

	cfg = __prepare_ICR2(mask);

	native_apic_mem_write(APIC_ICR2, cfg);



	/*

	 * program the ICR

	 */

	cfg = __prepare_ICR(0, vector, dest);



	/*

	 * Send the IPI. The write to APIC_ICR fires this off.

	 */

	native_apic_mem_write(APIC_ICR, cfg);

}

void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest);



extern void default_send_IPI_single(int cpu, int vector);

extern void default_send_IPI_single_phys(int cpu, int vector);

arch/x86/kernel/apic/ipi.c

+60 −0
Original line number Diff line number Diff line
@@ -18,6 +18,66 @@ 
#include <asm/proto.h>

#include <asm/ipi.h>



void __default_send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest)

{

	/*

	 * Subtle. In the case of the 'never do double writes' workaround

	 * we have to lock out interrupts to be safe.  As we don't care

	 * of the value read we use an atomic rmw access to avoid costly

	 * cli/sti.  Otherwise we use an even cheaper single atomic write

	 * to the APIC.

	 */

	unsigned int cfg;



	/*

	 * Wait for idle.

	 */

	__xapic_wait_icr_idle();



	/*

	 * No need to touch the target chip field

	 */

	cfg = __prepare_ICR(shortcut, vector, dest);



	/*

	 * Send the IPI. The write to APIC_ICR fires this off.

	 */

	native_apic_mem_write(APIC_ICR, cfg);

}



/*

 * This is used to send an IPI with no shorthand notation (the destination is

 * specified in bits 56 to 63 of the ICR).

 */

void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)

{

	unsigned long cfg;



	/*

	 * Wait for idle.

	 */

	if (unlikely(vector == NMI_VECTOR))

		safe_apic_wait_icr_idle();

	else

		__xapic_wait_icr_idle();



	/*

	 * prepare target chip field

	 */

	cfg = __prepare_ICR2(mask);

	native_apic_mem_write(APIC_ICR2, cfg);



	/*

	 * program the ICR

	 */

	cfg = __prepare_ICR(0, vector, dest);



	/*

	 * Send the IPI. The write to APIC_ICR fires this off.

	 */

	native_apic_mem_write(APIC_ICR, cfg);

}



void default_send_IPI_single_phys(int cpu, int vector)

{

	unsigned long flags;