Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1a55361e authored by Lee Jones's avatar Lee Jones
Browse files

Merge branch 'ib-mfd-omap' into HEAD

parents 507792c9 2e1b365c

Documentation/devicetree/bindings/mfd/omap-usb-host.txt

+23 −0
Original line number Diff line number Diff line
@@ -32,6 +32,29 @@ Optional properties: 
- single-ulpi-bypass: Must be present if the controller contains a single

  ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1



- clocks: a list of phandles and clock-specifier pairs, one for each entry in

  clock-names.



- clock-names: should include:

  For OMAP3

  * "usbhost_120m_fck" - 120MHz Functional clock.



  For OMAP4+

  * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux

  * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.

  * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux

  * "utmi_p1_gfclk" - Port 1 UTMI clock mux.

  * "utmi_p2_gfclk" - Port 2 UTMI clock mux.

  * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.

  * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.

  * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.

  * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.

  * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.

  * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.

  * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.

  * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.

  * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.



Required properties if child node exists:



- #address-cells: Must be 1

Documentation/devicetree/bindings/mfd/omap-usb-tll.txt

+10 −0
Original line number Diff line number Diff line
@@ -7,6 +7,16 @@ Required properties: 
- interrupts : should contain the TLL module's interrupt

- ti,hwmod : must contain "usb_tll_hs"



Optional properties:



- clocks: a list of phandles and clock-specifier pairs, one for each entry in

  clock-names.



- clock-names: should include:

  * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock

  * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock

  * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock



Example:



	usbhstll: usbhstll@4a062000 {

arch/arm/boot/dts/omap4.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -697,6 +697,12 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			clocks = <&init_60m_fclk>,

				 <&xclk60mhsp1_ck>,

				 <&xclk60mhsp2_ck>;

			clock-names = "refclk_60m_int",

				      "refclk_60m_ext_p1",

				      "refclk_60m_ext_p2";



			usbhsohci: ohci@4a064800 {

				compatible = "ti,ohci-omap3", "usb-ohci";

arch/arm/boot/dts/omap5.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -775,6 +775,12 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			clocks = <&l3init_60m_fclk>,

				 <&xclk60mhsp1_ck>,

				 <&xclk60mhsp2_ck>;

			clock-names = "refclk_60m_int",

				      "refclk_60m_ext_p1",

				      "refclk_60m_ext_p2";



			usbhsohci: ohci@4a064800 {

				compatible = "ti,ohci-omap3", "usb-ohci";

arch/arm/mach-omap2/cclock3xxx_data.c

+0 −4
Original line number Diff line number Diff line
@@ -3495,10 +3495,6 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK(NULL,	"dss_tv_fck",	&dss_tv_fck),

	CLK(NULL,	"dss_96m_fck",	&dss_96m_fck),

	CLK(NULL,	"dss2_alwon_fck",	&dss2_alwon_fck),

	CLK(NULL,	"utmi_p1_gfclk",	&dummy_ck),

	CLK(NULL,	"utmi_p2_gfclk",	&dummy_ck),

	CLK(NULL,	"xclk60mhsp1_ck",	&dummy_ck),

	CLK(NULL,	"xclk60mhsp2_ck",	&dummy_ck),

	CLK(NULL,	"init_60m_fclk",	&dummy_ck),

	CLK(NULL,	"gpt1_fck",	&gpt1_fck),

	CLK(NULL,	"aes2_ick",	&aes2_ick),