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Commit 19bc2eec authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux 

Pull clock framework changes from Mike Turquette:
 "The clock framework changes for 3.15 look similar to past pull
  requests.  Mostly clock driver updates, more Device Tree support in
  the form of common functions useful across platforms and a handful of
  features and fixes to the framework core"

* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: shmobile: fix setting paretn clock rate
  clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
  clk: Fix minor errors in of_clk_init() function comments
  clk: reverse default clk provider initialization order in of_clk_init()
  clk: sirf: update copyright years to 2014
  clk: mmp: try to use closer one when do round rate
  clk: mmp: fix the wrong calculation formula
  clk: mmp: fix wrong mask when calculate denominator
  clk: st: Adds quadfs clock binding
  clk: st: Adds clockgen-vcc and clockgen-mux clock binding
  clk: st: Adds clockgen clock binding
  clk: st: Adds divmux and prediv clock binding
  clk: st: Support for A9 MUX clocks
  clk: st: Support for ClockGenA9/DDR/GPU
  clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
  clk: st: Support for VCC-mux and MUX clocks
  clk: st: Support for PLLs inside ClockGenA(s)
  clk: st: Support for DIVMUX and PreDiv Clocks
  clk: support hardware-specific debugfs entries
  clk: s2mps11: Use of_get_child_by_name
  ...
parents 9712d3c3 e44df332

Documentation/clk.txt

+34 −0
Original line number Diff line number Diff line
@@ -255,3 +255,37 @@ are sorted out. 


To bypass this disabling, include "clk_ignore_unused" in the bootargs to the

kernel.



	Part 7 - Locking



The common clock framework uses two global locks, the prepare lock and the

enable lock.



The enable lock is a spinlock and is held across calls to the .enable,

.disable and .is_enabled operations. Those operations are thus not allowed to

sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API

functions are allowed in atomic context.



The prepare lock is a mutex and is held across calls to all other operations.

All those operations are allowed to sleep, and calls to the corresponding API

functions are not allowed in atomic context.



This effectively divides operations in two groups from a locking perspective.



Drivers don't need to manually protect resources shared between the operations

of one group, regardless of whether those resources are shared by multiple

clocks or not. However, access to resources that are shared between operations

of the two groups needs to be protected by the drivers. An example of such a

resource would be a register that controls both the clock rate and the clock

enable/disable state.



The clock framework is reentrant, in that a driver is allowed to call clock

framework functions from within its implementation of clock operations. This

can for instance cause a .set_rate operation of one clock being called from

within the .set_rate operation of another clock. This case must be considered

in the driver implementations, but the code flow is usually controlled by the

driver in that case.



Note that locking must also be considered when code outside of the common

clock framework needs to access resources used by the clock operations. This

is considered out of scope of this document.

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

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Original line number Diff line number Diff line
@@ -30,3 +30,17 @@ Example: 
		resume-offset = <0x308>;

		reboot-offset = <0x4>;

	};



PCTRL: Peripheral misc control register



Required Properties:

- compatible: "hisilicon,pctrl"

- reg: Address and size of pctrl.



Example:



	/* for Hi3620 */

	pctrl: pctrl@fca09000 {

		compatible = "hisilicon,pctrl";

		reg = <0xfca09000 0x1000>;

	};

Documentation/devicetree/bindings/clock/altr_socfpga.txt

+5 −0
Original line number Diff line number Diff line
@@ -23,3 +23,8 @@ Optional properties: 
        and the bit index.

- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,

        and width.

- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls

	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second

	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

	hold/delay times that is needed for the SD/MMC CIU clock. The values of both

	can be 0-315 degrees, in 45 degree increments.

Documentation/devicetree/bindings/clock/axi-clkgen.txt

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ This binding uses the common clock binding[1]. 
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "adi,axi-clkgen".

- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".

- #clock-cells : from common clock binding; Should always be set to 0.

- reg : Address and length of the axi-clkgen register set.

- clocks : Phandle and clock specifier for the parent clock.

Documentation/devicetree/bindings/clock/clock-bindings.txt

+17 −0
Original line number Diff line number Diff line
@@ -44,6 +44,23 @@ For example: 
  clocks by index. The names should reflect the clock output signal

  names for the device.



clock-indices:	   If the identifyng number for the clocks in the node

		   is not linear from zero, then the this mapping allows

		   the mapping of identifiers into the clock-output-names

		   array.



For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:



	oscillator {

		compatible = "myclocktype";

		#clock-cells = <1>;

		clock-indices = <1>, <3>;

		clock-output-names = "clka", "clkb";

	}



	This ensures we do not have any empty nodes in clock-output-names





==Clock consumers==



Required properties: