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Commit 198bb4ce authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: Add function for flushing the TLB using the TLBINV instruction 



Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6136/
parent b0d4d300

arch/mips/include/asm/mipsregs.h

+13 −0
Original line number Diff line number Diff line
@@ -704,6 +704,19 @@ static inline int mm_insn_16bit(u16 insn) 
	return (opcode >= 1 && opcode <= 3) ? 1 : 0;

}



/*

 * TLB Invalidate Flush

 */

static inline void tlbinvf(void)

{

	__asm__ __volatile__(

		".set push\n\t"

		".set noreorder\n\t"

		".word 0x42000004\n\t" /* tlbinvf */

		".set pop");

}





/*

 * Functions to access the R10000 performance counters.	 These are basically

 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit