Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 19543a34 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add node to disable div2 clk switch for kona and lito"

parents 994e86c6 d0bbafe1
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -100,6 +100,9 @@ Required properties:
			 required to be configured to receive interrupts
			 in BCL block of WSA macro

Optional properties:
 - qcom,disable-div2-clk-switch: u32 int to disable clock switch for rx master.

Example:

&bolero {
+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@
				<4 LO 0x1>, <5 DSD_L 0x1>,
				<5 DSD_R 0x2>;
			qcom,swr-num-dev = <1>;
			qcom,disable-div2-clk-switch = <1>;
			qcom,swr-clock-stop-mode0 = <1>;
			wcd937x_rx_slave: wcd937x-rx-slave {
				compatible = "qcom,wcd937x-slave";
+1 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@
			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <5>;
			qcom,disable-div2-clk-switch = <1>;
			qcom,swr-port-mapping = <1 HPH_L 0x1>,
				<1 HPH_R 0x2>, <2 CLSH 0x1>,
				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@
			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <5>;
			qcom,disable-div2-clk-switch = <1>;
			qcom,swr-port-mapping = <1 HPH_L 0x1>,
				<1 HPH_R 0x2>, <2 CLSH 0x1>,
				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <5>;
			qcom,disable-div2-clk-switch = <1>;
			qcom,swr-port-mapping = <1 HPH_L 0x1>,
				<1 HPH_R 0x2>, <2 CLSH 0x1>,
				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
Loading