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Commit 18a8d499 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes contain the usual driver additions,
  enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
  devices.

  Additionally the framework core underwent a bit of surgery with two
  major changes:

   - The boundary between the clock core and clock providers (e.g clock
     drivers) is now more well defined with dedicated provider helper
     functions.  struct clk no longer maps 1:1 with the hardware clock
     but is a true per-user cookie which helps us tracker users of
     hardware clocks and debug bad behavior.

   - The addition of rate constraints for clocks.  Rate ranges are now
     supported which are analogous to the voltage ranges in the
     regulator framework.

  Unfortunately these changes to the core created some breakeage.  We
  think we fixed it all up but for this reason there are lots of last
  minute commits trying to undo the damage"

* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
  clk: Only recalculate the rate if needed
  Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
  clk: qoriq: Add support for the platform PLL
  powerpc/corenet: Enable CLK_QORIQ
  clk: Replace explicit clk assignment with __clk_hw_set_clk
  clk: Add __clk_hw_set_clk helper function
  clk: Don't dereference parent clock if is NULL
  MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
  clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
  clk: shmobile: div6: Avoid division by zero in .round_rate()
  clk: mxs: Fix invalid 32-bit access to frac registers
  clk: omap: compile legacy omap3 clocks conditionally
  clkdev: Export clk_register_clkdev
  clk: Add rate constraints to clocks
  clk: remove clk-private.h
  pci: xgene: do not use clk-private.h
  arm: omap2+ remove dead clock code
  clk: Make clk API return per-user struct clk instances
  clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
  clk: tegra: Add support for the Tegra132 CAR IP block
  ...
parents c189cb8e ec02ace8
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@@ -73,6 +73,8 @@ the operations defined in clk.h:
						unsigned long *parent_rate);
		long		(*determine_rate)(struct clk_hw *hw,
						unsigned long rate,
						unsigned long min_rate,
						unsigned long max_rate,
						unsigned long *best_parent_rate,
						struct clk_hw **best_parent_clk);
		int		(*set_parent)(struct clk_hw *hw, u8 index);
+15 −0
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@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
	- "samsung,exynos7-clock-peris"
	- "samsung,exynos7-clock-fsys0"
	- "samsung,exynos7-clock-fsys1"
	- "samsung,exynos7-clock-mscl"
	- "samsung,exynos7-clock-aud"

 - reg: physical base address of the controller and the length of
	memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
	- dout_sclk_bus1_pll
	- dout_sclk_cc_pll
	- dout_sclk_mfc_pll
	- dout_sclk_aud_pll

Input clocks for top1 clock controller:
	- fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
	- sclk_uart1
	- sclk_uart2
	- sclk_uart3
	- sclk_spi0
	- sclk_spi1
	- sclk_spi2
	- sclk_spi3
	- sclk_spi4
	- sclk_i2s1
	- sclk_pcm1
	- sclk_spdif

Input clocks for peris clock controller:
	- fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
	- dout_aclk_fsys1_200
	- dout_sclk_mmc0
	- dout_sclk_mmc1

Input clocks for aud clock controller:
	- fin_pll
	- fout_aud_pll
+6 −4
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NVIDIA Tegra124 Clock And Reset Controller
NVIDIA Tegra124 and Tegra132 Clock And Reset Controller

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.

Required properties :
- compatible : Should be "nvidia,tegra124-car"
- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
  In clock consumers, this cell represents the clock ID exposed by the
  CAR. The assignments may be found in header file
  <dt-bindings/clock/tegra124-car.h>.
  CAR. The assignments may be found in the header files
  <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
  to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
  (for Tegra124-specific clocks).
- #reset-cells : Should be 1.
  In clock consumers, this cell represents the bit number in the CAR's
  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
+21 −0
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Qualcomm LPASS Clock & Reset Controller Binding
------------------------------------------------

Required properties :
- compatible : shall contain only one of the following:

			"qcom,lcc-msm8960"
			"qcom,lcc-apq8064"
			"qcom,lcc-ipq8064"

- reg : shall contain base register location and length
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1

Example:
	clock-controller@28000000 {
		compatible = "qcom,lcc-ipq8064";
		reg = <0x28000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};
+3 −2
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* Clock Block on Freescale CoreNet Platforms
* Clock Block on Freescale QorIQ Platforms

Freescale CoreNet chips take primary clocking input from the external
Freescale qoriq chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
	* "fsl,t4240-clockgen"
	* "fsl,b4420-clockgen"
	* "fsl,b4860-clockgen"
	* "fsl,ls1021a-clockgen"
	Chassis clock strings include:
	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
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