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Commit 18a8067c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Assert the dbuf is enabled when disabling DC5/6 



Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
Let's make sure it has correctly restored the dbuf state to enabled
when we disable the DC states.

v2: s/skl/gen9/ in function name (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Suggested-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463407180-28993-1-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent d1b32c32

drivers/gpu/drm/i915/intel_runtime_pm.c

+11 −0
Original line number Diff line number Diff line
@@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 
	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;

}



static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)

{

	u32 tmp = I915_READ(DBUF_CTL);



	WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=

	     (DBUF_POWER_STATE | DBUF_POWER_REQUEST),

	     "Unexpected DBuf power power state (0x%08x)\n", tmp);

}



static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,

					  struct i915_power_well *power_well)

{
@@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 
	WARN_ON(dev_priv->cdclk_freq !=

		dev_priv->display.get_display_clock_speed(dev_priv->dev));



	gen9_assert_dbuf_enabled(dev_priv);



	if (IS_BROXTON(dev_priv))

		broxton_ddi_phy_verify_state(dev_priv);

}