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Commit 1854b430 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Fix incorrect length in GPU Powerup list for A6x GPU"

parents 2613885a f6ebc9f7

drivers/gpu/msm/adreno_a6xx.c

+4 −4
Original line number Diff line number Diff line
@@ -802,7 +802,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
			+ sizeof(a6xx_pwrup_reglist), a615_pwrup_reglist,

			sizeof(a615_pwrup_reglist));



		lock->list_length += sizeof(a615_pwrup_reglist);

		lock->list_length += sizeof(a615_pwrup_reglist) >> 2;

	}

}
@@ -1649,7 +1649,7 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
		gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS)

			| gpu_scid;



	if (adreno_is_a640(adreno_dev)) {

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev)) {

		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

	} else {
@@ -1671,7 +1671,7 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 
	 * On A640, the GPUHTW SCID is configured via a NoC override in the

	 * XBL image.

	 */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		return;



	gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);
@@ -1692,7 +1692,7 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) 
	 * Attributes override through GBIF is not supported with MMU-500.

	 * Attributes are used as configured through SMMU pagetable entries.

	 */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		return;



	/*

drivers/gpu/msm/adreno_a6xx_rgmu.c

+2 −4
Original line number Diff line number Diff line
@@ -103,8 +103,7 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device, 
	struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);

	int ret, set, check;



	/* Return silently for unsupported OOBs */

	if (!gmu_core_isenabled(device) || req > oob_gpu)

	if (!gmu_core_isenabled(device))

		return 0;



	set = BIT(req + 16);
@@ -141,8 +140,7 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device, 
static inline void a6xx_rgmu_oob_clear(struct kgsl_device *device,

		enum oob_request req)

{

	/* Return silently for unsupported OOBs */

	if (!gmu_core_isenabled(device) || req > oob_gpu)

	if (!gmu_core_isenabled(device))

		return;



	gmu_core_regwrite(device, A6XX_GMU_HOST2GMU_INTR_SET, BIT(req + 24));

drivers/gpu/msm/kgsl_iommu.c

+1 −1
Original line number Diff line number Diff line
@@ -1177,7 +1177,7 @@ void _enable_gpuhtw_llc(struct kgsl_mmu *mmu, struct kgsl_iommu_pt *iommu_pt) 
		return;



	/* Domain attribute to enable system cache for GPU pagetable walks */

	if (adreno_is_a640(adreno_dev))

	if (adreno_is_a640(adreno_dev) || adreno_is_a608(adreno_dev))

		ret = iommu_domain_set_attr(iommu_pt->domain,

			DOMAIN_ATTR_USE_LLC_NWA, &gpuhtw_llc_enable);

	else