Commit 179eb850 authored Dec 18, 2017 by Yazen Ghannam Committed by Thomas Gleixner Dec 18, 2017

x86/MCE: Make correctable error detection look at the Deferred bit



AMD systems may log Deferred errors. These are errors that are uncorrected
but which do not need immediate action. The MCA_STATUS[UC] bit may not be
set for Deferred errors.

Flag the error as not correctable when MCA_STATUS[Deferred] is set and
do not feed it into the Correctable Errors Collector.

[ bp: Massage commit message. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20171212165143.27475-1-Yazen.Ghannam@amd.com

parent c6708d50

arch/x86/kernel/cpu/mcheck/mce.c

+12 −1

Original line number	Diff line number	Diff line
		@@ -528,6 +528,17 @@ bool mce_is_memory_error(struct mce *m)
		}
		EXPORT_SYMBOL_GPL(mce_is_memory_error);

		static bool mce_is_correctable(struct mce *m)
		{
		if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
		return false;

		if (m->status & MCI_STATUS_UC)
		return false;

		return true;
		}

		static bool cec_add_mce(struct mce *m)
		{
		if (!m)
		@@ -535,7 +546,7 @@ static bool cec_add_mce(struct mce *m)

		/* We eat only correctable DRAM errors with usable addresses. */
		if (mce_is_memory_error(m) &&
		!(m->status & MCI_STATUS_UC) &&
		mce_is_correctable(m) &&
		mce_usable_address(m))
		if (!cec_add_elem(m->addr >> PAGE_SHIFT))
		return true;