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Commit 17465149 authored by Wolfram Sang's avatar Wolfram Sang Committed by Simon Horman
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ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi 



Signed-off-by: default avatarWolfram Sang <wsa@sang-engineering.com>
[horms+renesas@verge.net.au resolved conflicts]
[horms+renesas@verge.net.au consistently use space as separator]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 01d968e9

arch/arm/boot/dts/r8a7790.dtsi

+14 −13
Original line number Diff line number Diff line
@@ -702,18 +702,19 @@ 
		mstp3_clks: mstp3_clks@e615013c {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

			clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,

				 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,

				 <&mmc0_clk>, <&rclk_clk>;

			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,

				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,

				 <&hp_clk>, <&hp_clk>, <&rclk_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0

				R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1

				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0

				R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1

			>;

			clock-output-names =

				"tpu0", "mmcif1", "sdhi3", "sdhi2",

				"sdhi1", "sdhi0", "mmcif0", "cmt1";

				"iic2", "tpu0", "mmcif1", "sdhi3",

				"sdhi2", "sdhi1", "sdhi0", "mmcif0",

				"iic0", "iic1", "cmt1";

		};

		mstp5_clks: mstp5_clks@e6150144 {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -757,16 +758,16 @@ 
		mstp9_clks: mstp9_clks@e6150994 {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;

			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,

			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,

				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD

				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1

				R8A7790_CLK_I2C0

				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS

				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0

			>;

			clock-output-names =

				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";

				"rcan1", "rcan0", "qspi_mod", "iic3",

				"i2c3", "i2c2", "i2c1", "i2c0";

		};

	};