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Commit 16e9ab82 authored by Lucas Stach's avatar Lucas Stach Committed by Philipp Zabel
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gpu: ipu-v3: prg: remove counter load enable 



The counter load enable bit has no effect when the shadow register
set is activated. As we always operate the PRG with shadow enabled
it is safe to remove this.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 2ea659a9

drivers/gpu/ipu-v3/ipu-prg.c

+0 −2
Original line number Diff line number Diff line
@@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan, 
	writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));



	val = readl(prg->regs + IPU_PRG_CTL);

	/* counter load enable */

	val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan);

	/* config AXI ID */

	val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<

		 IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));