Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit 16c10b3b authored by Mark Brown's avatar Mark Brown
Browse files

Merge branch 'spi-4.17' into spi-4.18 for the merge window

parents 29e795ca 0921e11e

drivers/spi/spi-bcm-qspi.c

+18 −10
Original line number Diff line number Diff line
@@ -488,7 +488,7 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, 


static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)

{

	if (!has_bspi(qspi) || (qspi->bspi_enabled))

	if (!has_bspi(qspi))

		return;



	qspi->bspi_enabled = 1;
@@ -503,7 +503,7 @@ static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) 


static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)

{

	if (!has_bspi(qspi) || (!qspi->bspi_enabled))

	if (!has_bspi(qspi))

		return;



	qspi->bspi_enabled = 0;
@@ -517,16 +517,19 @@ static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) 


static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)

{

	u32 data = 0;

	u32 rd = 0;

	u32 wr = 0;



	if (qspi->curr_cs == cs)

		return;

	if (qspi->base[CHIP_SELECT]) {

		data = bcm_qspi_read(qspi, CHIP_SELECT, 0);

		data = (data & ~0xff) | (1 << cs);

		bcm_qspi_write(qspi, CHIP_SELECT, 0, data);

		rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);

		wr = (rd & ~0xff) | (1 << cs);

		if (rd == wr)

			return;

		bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);

		usleep_range(10, 20);

	}



	dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);

	qspi->curr_cs = cs;

}
@@ -753,8 +756,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) 
			dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);

		}

		mspi_cdram = MSPI_CDRAM_CONT_BIT;



		if (has_bspi(qspi))

			mspi_cdram &= ~1;

		else

			mspi_cdram |= (~(1 << spi->chip_select) &

				       MSPI_CDRAM_PCS);



		mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :

				MSPI_CDRAM_BITSE_BIT);

drivers/spi/spi-bcm2835aux.c

+5 −0
Original line number Diff line number Diff line
@@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) 
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	irqreturn_t ret = IRQ_NONE;



	/* IRQ may be shared, so return if our interrupts are disabled */

	if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &

	      (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))

		return ret;



	/* check if we have data to read */

	while (bs->rx_len &&

	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &

drivers/spi/spi-cadence.c

+8 −0
Original line number Diff line number Diff line
@@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) 


	while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&

	       (xspi->tx_bytes > 0)) {



		/* When xspi in busy condition, bytes may send failed,

		 * then spi control did't work thoroughly, add one byte delay

		 */

		if (cdns_spi_read(xspi, CDNS_SPI_ISR) &

		    CDNS_SPI_IXR_TXFULL)

			usleep_range(10, 20);



		if (xspi->txbuf)

			cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);

		else

drivers/spi/spi-sh-msiof.c

+4 −2
Original line number Diff line number Diff line
@@ -567,14 +567,16 @@ static int sh_msiof_spi_setup(struct spi_device *spi) 


	/* Configure native chip select mode/polarity early */

	clr = MDR1_SYNCMD_MASK;

	set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;

	set = MDR1_SYNCMD_SPI;

	if (spi->mode & SPI_CS_HIGH)

		clr |= BIT(MDR1_SYNCAC_SHIFT);

	else

		set |= BIT(MDR1_SYNCAC_SHIFT);

	pm_runtime_get_sync(&p->pdev->dev);

	tmp = sh_msiof_read(p, TMDR1) & ~clr;

	sh_msiof_write(p, TMDR1, tmp | set);

	sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);

	tmp = sh_msiof_read(p, RMDR1) & ~clr;

	sh_msiof_write(p, RMDR1, tmp | set);

	pm_runtime_put(&p->pdev->dev);

	p->native_cs_high = spi->mode & SPI_CS_HIGH;

	p->native_cs_inited = true;