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Commit 16bf8348 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull trivial tree updates from Jiri Kosina.

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (21 commits)
  gitignore: fix wording
  mfd: ab8500-debugfs: fix "between" in printk
  memstick: trivial fix of spelling mistake on management
  cpupowerutils: bench: fix "average"
  treewide: Fix typos in printk
  IB/mlx4: printk fix
  pinctrl: sirf/atlas7: fix printk spelling
  serial: mctrl_gpio: Grammar s/lines GPIOs/line GPIOs/, /sets/set/
  w1: comment spelling s/minmum/minimum/
  Blackfin: comment spelling s/divsor/divisor/
  metag: Fix misspellings in comments.
  ia64: Fix misspellings in comments.
  hexagon: Fix misspellings in comments.
  tools/perf: Fix misspellings in comments.
  cris: Fix misspellings in comments.
  c6x: Fix misspellings in comments.
  blackfin: Fix misspelling of 'register' in comment.
  avr32: Fix misspelling of 'definitions' in comment.
  treewide: Fix typos in printk
  Doc: treewide : Fix typos in DocBook/filesystem.xml
  ...
parents a7fd20d1 52bbe141
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@@ -62,7 +62,7 @@ Module.symvers
/tar-install/

#
# git files that we don't want to ignore even it they are dot-files
# git files that we don't want to ignore even if they are dot-files
#
!.gitignore
!.mailmap
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/*
 * Defitions for the address spaces of the AVR32 CPUs. Heavily based on
 * Definitions for the address spaces of the AVR32 CPUs. Heavily based on
 * include/asm-sh/addrspace.h
 *
 * Copyright (C) 2004-2006 Atmel Corporation
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@@ -154,7 +154,7 @@ ENTRY(___udivsi3)
       CC = R7 < 0;               /* Check quotient(AQ) */
                                  /* If AQ==0, we'll sub divisor */
       IF CC R5 = R1;             /* and if AQ==1, we'll add it. */
       R3 = R3 + R5;              /* Add/sub divsor to partial remainder */
       R3 = R3 + R5;              /* Add/sub divisor to partial remainder */
       R7 = R3 ^ R1;              /* Generate next quotient bit */

       R5 = R7 >> 31;             /* Get AQ */
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@@ -2689,7 +2689,7 @@
#define L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 L2 Status Register */
#define L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 L2 Read Priority Count Register */
#define L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 L2 Write Priority Count Register */
#define L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Regsiter */
#define L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Register */
#define L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 L2 Bank 0 ECC Error Address Register */
#define L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 L2 Bank 1 ECC Error Address Register */
#define L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 L2 Bank 2 ECC Error Address Register */
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@@ -101,7 +101,7 @@ struct clk {
#define CLK_PLL			BIT(2) /* PLL-derived clock */
#define PRE_PLL			BIT(3) /* source is before PLL mult/div */
#define FIXED_DIV_PLL		BIT(4) /* fixed divisor from PLL */
#define FIXED_RATE_PLL		BIT(5) /* fixed ouput rate PLL */
#define FIXED_RATE_PLL		BIT(5) /* fixed output rate PLL */

#define MAX_PLL_SYSCLKS 16

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