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Commit 164dfd28 authored by Vandana Kannan's avatar Vandana Kannan Committed by Daniel Vetter
Browse files

drm/i915: Rename vlv_cdclk_freq to cdclk_freq 



Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
platforms as required. Needed by the next patch.

Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c7240c3b

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1656,7 +1656,7 @@ struct drm_i915_private { 
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */



	unsigned int fsb_freq, mem_freq, is_ddr3;

	unsigned int vlv_cdclk_freq;

	unsigned int cdclk_freq;

	unsigned int hpll_freq;



	/**

drivers/gpu/drm/i915/intel_display.c

+10 −8
Original line number Diff line number Diff line
@@ -5214,16 +5214,16 @@ static void vlv_update_cdclk(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);

	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);

	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",

			 dev_priv->vlv_cdclk_freq);

			 dev_priv->cdclk_freq);



	/*

	 * Program the gmbus_freq based on the cdclk frequency.

	 * BSpec erroneously claims we should aim for 4MHz, but

	 * in fact 1MHz is the correct frequency.

	 */

	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));

	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));

}



/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -5232,7 +5232,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val, cmd;



	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);

	WARN_ON(dev_priv->display.get_display_clock_speed(dev)

					!= dev_priv->cdclk_freq);



	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */

		cmd = 2;
@@ -5296,7 +5297,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val, cmd;



	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);

	WARN_ON(dev_priv->display.get_display_clock_speed(dev)

						!= dev_priv->cdclk_freq);



	switch (cdclk) {

	case 333333:
@@ -5395,7 +5397,7 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, 
		return max_pixclk;



	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==

	    dev_priv->vlv_cdclk_freq)

	    dev_priv->cdclk_freq)

		return 0;



	/* disable/enable all currently active pipes while we change cdclk */
@@ -5415,7 +5417,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 
	else

		default_credits = PFI_CREDIT(8);



	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {

	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {

		/* CHV suggested value is 31 or 63 */

		if (IS_CHERRYVIEW(dev_priv))

			credits = PFI_CREDIT_31;
@@ -5459,7 +5461,7 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *state) 


	req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);



	if (req_cdclk != dev_priv->vlv_cdclk_freq) {

	if (req_cdclk != dev_priv->cdclk_freq) {

		/*

		 * FIXME: We can end up here with all power domains off, yet

		 * with a CDCLK frequency other than the minimum. To account