clk: qcom: Add support for Video clock driver for LAGOON (15692aab) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/Kconfig

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		@@ -451,3 +451,12 @@ config SDM_GCC_LAGOON
		LAGOON devices.
		Say Y if you want to use peripheral devices such as UART, SPI, I2C,
		USB, UFS, SD/eMMC, etc.

		config SDM_VIDEOCC_LAGOON
		tristate "LAGOON Video Clock Controller"
		select SDM_GCC_LAGOON
		help
		Support for the video clock controller on Qualcomm Technologies, Inc.
		LAGOON devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.

drivers/clk/qcom/Makefile

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		@@ -53,6 +53,7 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
		obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
		obj-$(CONFIG_SDM_GCC_LAGOON) += gcc-lagoon.o
		obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
		obj-$(CONFIG_SDM_VIDEOCC_LAGOON) += videocc-lagoon.o
		obj-$(CONFIG_SM_CAMCC_LITO) += camcc-lito.o
		obj-$(CONFIG_SM_DEBUGCC_BENGAL) += debugcc-bengal.o
		obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o

drivers/clk/qcom/videocc-lagoon.c

0 → 100644

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		*/

		#define pr_fmt(fmt) "clk: %s: " fmt, __func__

		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/err.h>
		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,videocc-lagoon.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-pll.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "common.h"
		#include "reset.h"
		#include "vdd-level-lito.h"

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CHIP_SLEEP_CLK,
		P_CORE_BI_PLL_TEST_SE,
		P_VIDEO_PLL0_OUT_EVEN,
		};

		static const struct parent_map video_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_PLL0_OUT_EVEN, 3 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const video_cc_parent_names_0[] = {
		"bi_tcxo",
		"video_pll0_out_even",
		"core_bi_pll_test_se",
		};

		static const struct parent_map video_cc_parent_map_1[] = {
		{ P_CHIP_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const video_cc_parent_names_1[] = {
		"chip_sleep_clk",
		"core_bi_pll_test_se",
		};

		static const struct parent_map video_cc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const video_cc_parent_names_2[] = {
		"bi_tcxo",
		"core_bi_pll_test_se",
		};

		static const struct pll_vco fabia_vco[] = {
		{ 125000000, 1000000000, 1 },
		};

		/* 600 MHz */
		static const struct alpha_pll_config video_pll0_config = {
		.l = 0x1F,
		.cal_l = 0x29,
		.alpha = 0x4000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		.test_ctl_val = 0x40000000,
		.test_ctl_hi_val = 0x00000000,
		.user_ctl_val = 0x00000101,
		.user_ctl_hi_val = 0x00004005,
		};

		static struct clk_alpha_pll video_pll0 = {
		.offset = 0x0,
		.vco_table = fabia_vco,
		.num_vco = ARRAY_SIZE(fabia_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "video_pll0",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_alpha_pll_fabia_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 615000000,
		[VDD_LOW] = 1066000000,
		[VDD_LOW_L1] = 1600000000,
		[VDD_NOMINAL] = 2000000000},
		},
		},
		};

		static const struct clk_div_table post_div_table_video_pll0_out_even[] = {
		{ 0x1, 2 },
		{ }
		};

		static struct clk_alpha_pll_postdiv video_pll0_out_even = {
		.offset = 0x0,
		.post_div_shift = 8,
		.post_div_table = post_div_table_video_pll0_out_even,
		.num_post_div = ARRAY_SIZE(post_div_table_video_pll0_out_even),
		.width = 4,
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_pll0_out_even",
		.parent_names = (const char *[]){ "video_pll0" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_alpha_pll_postdiv_fabia_ops,
		},
		};

		static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(133250000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
		F(240000000, P_VIDEO_PLL0_OUT_EVEN, 1.5, 0, 0),
		F(300000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0),
		F(380000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0),
		F(460000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_iris_clk_src = {
		.cmd_rcgr = 0x1000,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_iris_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_iris_clk_src",
		.parent_names = video_cc_parent_names_0,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 133250000,
		[VDD_LOW] = 240000000,
		[VDD_LOW_L1] = 300000000,
		[VDD_NOMINAL] = 380000000,
		[VDD_HIGH] = 460000000},
		},
		};

		static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
		F(32764, P_CHIP_SLEEP_CLK, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_sleep_clk_src = {
		.cmd_rcgr = 0x701c,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_1,
		.freq_tbl = ftbl_video_cc_sleep_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk_src",
		.parent_names = video_cc_parent_names_1,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 32764},
		},
		};

		static struct clk_branch video_cc_iris_ahb_clk = {
		.halt_reg = 0x5004,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x5004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_iris_ahb_clk",
		.parent_names = (const char *[]){
		"video_cc_iris_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_axi_clk = {
		.halt_reg = 0x800c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x800c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_core_clk = {
		.halt_reg = 0x3010,
		.halt_check = BRANCH_VOTED,
		.hwcg_reg = 0x3010,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x3010,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_core_clk",
		.parent_names = (const char *[]){
		"video_cc_iris_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvsc_core_clk = {
		.halt_reg = 0x2014,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2014,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvsc_core_clk",
		.parent_names = (const char *[]){
		"video_cc_iris_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
		.halt_reg = 0x8004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvsc_ctl_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_sleep_clk = {
		.halt_reg = 0x7034,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7034,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk",
		.parent_names = (const char *[]){
		"video_cc_sleep_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_venus_ahb_clk = {
		.halt_reg = 0x801c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x801c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_venus_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_xo_clk = {
		.halt_reg = 0x7018,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7018,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_xo_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_regmap *video_cc_lagoon_clocks[] = {
		[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
		[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
		[VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr,
		[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
		[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
		[VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr,
		[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
		[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
		[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
		[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
		[VIDEO_PLL0] = &video_pll0.clkr,
		[VIDEO_PLL0_OUT_EVEN] = &video_pll0_out_even.clkr,
		};

		static const struct qcom_reset_map video_cc_lito_resets[] = {
		[VCODEC_VIDEO_CC_INTERFACE_BCR] = { 0x8000 },
		[VCODEC_VIDEO_CC_MVS0_BCR] = { 0x3000 },
		[VCODEC_VIDEO_CC_MVSC_BCR] = { 0x2000 },
		};

		static const struct regmap_config video_cc_lagoon_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0xb000,
		.fast_io = true,
		};

		static const struct qcom_cc_desc video_cc_lagoon_desc = {
		.config = &video_cc_lagoon_regmap_config,
		.clks = video_cc_lagoon_clocks,
		.num_clks = ARRAY_SIZE(video_cc_lagoon_clocks),
		};

		static const struct of_device_id video_cc_lagoon_match_table[] = {
		{ .compatible = "qcom,lagoon-videocc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, video_cc_lagoon_match_table);

		static int video_cc_lagoon_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		struct clk *clk;
		int ret;

		clk = devm_clk_get(&pdev->dev, "cfg_ahb_clk");
		if (IS_ERR(clk)) {
		if (PTR_ERR(clk) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
		return PTR_ERR(clk);
		}
		devm_clk_put(&pdev->dev, clk);

		vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
		if (IS_ERR(vdd_cx.regulator[0])) {
		if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
		dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
		return PTR_ERR(vdd_cx.regulator[0]);
		}

		regmap = qcom_cc_map(pdev, &video_cc_lagoon_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);

		ret = qcom_cc_really_probe(pdev, &video_cc_lagoon_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
		return ret;
		}

		dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");

		return ret;
		}

		static struct platform_driver video_cc_lagoon_driver = {
		.probe = video_cc_lagoon_probe,
		.driver = {
		.name = "video_cc-lagoon",
		.of_match_table = video_cc_lagoon_match_table,
		},
		};

		static int __init video_cc_lagoon_init(void)
		{
		return platform_driver_register(&video_cc_lagoon_driver);
		}
		core_initcall(video_cc_lagoon_init);

		static void __exit video_cc_lagoon_exit(void)
		{
		platform_driver_unregister(&video_cc_lagoon_driver);
		}
		module_exit(video_cc_lagoon_exit);

		MODULE_DESCRIPTION("QTI VIDEO_CC LAGOON Driver");
		MODULE_LICENSE("GPL v2");