Blackfin arch: add sdh support for bf518f-ezbrd

#define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)

#define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)

#define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)

#define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)

/* Removable Storage Interface Registers */

#define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)

#define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)

#define bfin_read_RSI_CLK_CTL()	       bfin_read16(RSI_CLK_CONTROL)

#define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)

#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)

#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)

#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)

#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)

#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)

#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)

#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)

#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)

#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)

#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)

#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)

#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)

#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)

#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)

#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)

#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)

#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)

#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)

#define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)

#define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)

#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)

#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)

#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)

#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)

#define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)

#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)

#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)

#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)

#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)

#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)

#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)

#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)

#define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)

#define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)

#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)

#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)

#define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)

#define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)

#define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)

#define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)

#define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)

#define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)

#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)

#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)

#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)

#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)

#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)

#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)

#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)

#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)

#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)

#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)

#define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)

#define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)

#define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)

#define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)

#define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)

#define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)

#define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)

#define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)

#endif /* _CDEF_BF518_H */

#endif /* _CDEF_BF518_H */

#define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */

#define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */

#define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */

#define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */

/* ********************************************************** */

/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */

/*     and MULTI BIT READ MACROS                              */

/* ********************************************************** */

/* Bit masks for SDH_COMMAND */

#define                   CMD_IDX  0x3f       /* Command Index */

#define                   CMD_RSP  0x40       /* Response */

#define                 CMD_L_RSP  0x80       /* Long Response */

#define                 CMD_INT_E  0x100      /* Command Interrupt */

#define                CMD_PEND_E  0x200      /* Command Pending */

#define                     CMD_E  0x400      /* Command Enable */

/* Bit masks for SDH_PWR_CTL */

#define                    PWR_ON  0x3        /* Power On */

#if 0

#define                       TBD  0x3c       /* TBD */

#endif

#define                 SD_CMD_OD  0x40       /* Open Drain Output */

#define                   ROD_CTL  0x80       /* Rod Control */

/* Bit masks for SDH_CLK_CTL */

#define                    CLKDIV  0xff       /* MC_CLK Divisor */

#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */

#define                  PWR_SV_E  0x200      /* Power Save Enable */

#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */

#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */

/* Bit masks for SDH_RESP_CMD */

#define                  RESP_CMD  0x3f       /* Response Command */

/* Bit masks for SDH_DATA_CTL */

#define                     DTX_E  0x1        /* Data Transfer Enable */

#define                   DTX_DIR  0x2        /* Data Transfer Direction */

#define                  DTX_MODE  0x4        /* Data Transfer Mode */

#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */

#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */

/* Bit masks for SDH_STATUS */

#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */

#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */

#define               CMD_TIME_OUT  0x4        /* CMD Time Out */

#define               DAT_TIME_OUT  0x8        /* Data Time Out */

#define               TX_UNDERRUN  0x10       /* Transmit Underrun */

#define                RX_OVERRUN  0x20       /* Receive Overrun */

#define              CMD_RESP_END  0x40       /* CMD Response End */

#define                  CMD_SENT  0x80       /* CMD Sent */

#define                   DAT_END  0x100      /* Data End */

#define             START_BIT_ERR  0x200      /* Start Bit Error */

#define               DAT_BLK_END  0x400      /* Data Block End */

#define                   CMD_ACT  0x800      /* CMD Active */

#define                    TX_ACT  0x1000     /* Transmit Active */

#define                    RX_ACT  0x2000     /* Receive Active */

#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */

#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */

#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */

#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */

#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */

#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */

#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */

#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */

/* Bit masks for SDH_STATUS_CLR */

#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */

#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */

#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */

#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */

#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */

#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */

#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */

#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */

#define              DAT_END_STAT  0x100      /* Data End Status */

#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */

#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */

/* Bit masks for SDH_MASK0 */

#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */

#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */

#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */

#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */

#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */

#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */

#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */

#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */

#define              DAT_END_MASK  0x100      /* Data End Mask */

#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */

#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */

#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */

#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */

#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */

#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */

#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */

#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */

#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */

#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */

#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */

#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */

#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */

/* Bit masks for SDH_FIFO_CNT */

#define                FIFO_COUNT  0x7fff     /* FIFO Count */

/* Bit masks for SDH_E_STATUS */

#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */

#define               SD_CARD_DET  0x10       /* SD Card Detect */

/* Bit masks for SDH_E_MASK */

#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */

#define                   SCD_MSK  0x40       /* Mask Card Detect */

/* Bit masks for SDH_CFG */

#define                   CLKS_EN  0x1        /* Clocks Enable */

#define                      SD4E  0x4        /* SDIO 4-Bit Enable */

#define                       MWE  0x8        /* Moving Window Enable */

#define                    SD_RST  0x10       /* SDMMC Reset */

#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */

#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */

#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */

/* Bit masks for SDH_RD_WAIT_EN */

#define                       RWR  0x1        /* Read Wait Request */

#endif /* _DEF_BF518_H */

#endif /* _DEF_BF518_H */