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Commit 14a94ebd authored by Michal Kalderon's avatar Michal Kalderon Committed by David S. Miller
Browse files

bnx2x: Add support in PF driver for RSC 



This provides PF-side support for VFs assigned to a VM running windows
2012 with the RSC feature enabled.

Signed-off-by: default avatarMichal Kalderon <michals@broadcom.com>
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ba72f32c

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

+1 −0
Original line number Diff line number Diff line
@@ -1270,6 +1270,7 @@ struct bnx2x_slowpath { 
	union {

		struct client_init_ramrod_data  init_data;

		struct client_update_ramrod_data update_data;

		struct tpa_update_ramrod_data tpa_data;

	} q_rdata;



	union {

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+17 −4
Original line number Diff line number Diff line
@@ -1814,6 +1814,11 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 
		drv_cmd = BNX2X_Q_CMD_EMPTY;

		break;



	case (RAMROD_CMD_ID_ETH_TPA_UPDATE):

		DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);

		drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;

		break;



	default:

		BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",

			  command, fp->index);
@@ -3644,10 +3649,18 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 
			cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |

				    HW_CID(bp, cid));



	type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;



	/* In some cases, type may already contain the func-id

	 * mainly in SRIOV related use cases, so we add it here only

	 * if it's not already set.

	 */

	if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {

		type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &

			SPE_HDR_CONN_TYPE;

		type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &

			 SPE_HDR_FUNCTION_ID);

	} else {

		type = cmd_type;

	}



	spe->hdr.type = cpu_to_le16(type);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

+102 −43
Original line number Diff line number Diff line
@@ -2277,11 +2277,11 @@ static int bnx2x_set_rx_mode_e2(struct bnx2x *bp, 
			 data->header.rule_cnt, p->rx_accept_flags,

			 p->tx_accept_flags);



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	/* Send a ramrod */
@@ -2982,11 +2982,11 @@ static int bnx2x_mcast_setup_e2(struct bnx2x *bp, 
		raw->clear_pending(raw);

		return 0;

	} else {

		/* No need for an explicit memory barrier here as long we would

		 * need to ensure the ordering of writing to the SPQ element

		/* No need for an explicit memory barrier here as long as we

		 * ensure the ordering of writing to the SPQ element

		 * and updating of the SPQ producer which involves a memory

		 * read and we will have to put a full memory barrier there

		 * (inside bnx2x_sp_post()).

		 * read. If the memory read is removed we will have to put a

		 * full memory barrier there (inside bnx2x_sp_post()).

		 */



		/* Send a ramrod */
@@ -3466,11 +3466,11 @@ static int bnx2x_mcast_setup_e1(struct bnx2x *bp, 
		raw->clear_pending(raw);

		return 0;

	} else {

		/* No need for an explicit memory barrier here as long we would

		 * need to ensure the ordering of writing to the SPQ element

		/* No need for an explicit memory barrier here as long as we

		 * ensure the ordering of writing to the SPQ element

		 * and updating of the SPQ producer which involves a memory

		 * read and we will have to put a full memory barrier there

		 * (inside bnx2x_sp_post()).

		 * read. If the memory read is removed we will have to put a

		 * full memory barrier there (inside bnx2x_sp_post()).

		 */



		/* Send a ramrod */
@@ -4091,11 +4091,11 @@ static int bnx2x_setup_rss(struct bnx2x *bp, 
		data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;

	}



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	/* Send a ramrod */
@@ -4587,13 +4587,12 @@ static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp, 
	/* Fill the ramrod data */

	bnx2x_q_fill_setup_data_cmn(bp, params, rdata);



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), ETH_CONNECTION_TYPE);
@@ -4615,13 +4614,12 @@ static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp, 
	bnx2x_q_fill_setup_data_cmn(bp, params, rdata);

	bnx2x_q_fill_setup_data_e2(bp, params, rdata);



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), ETH_CONNECTION_TYPE);
@@ -4659,13 +4657,12 @@ static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp, 
			 o->cids[cid_index], rdata->general.client_id,

			 rdata->general.sp_client_id, rdata->general.cos);



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	return bnx2x_sp_post(bp, ramrod, o->cids[cid_index],

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), ETH_CONNECTION_TYPE);
@@ -4760,13 +4757,12 @@ static inline int bnx2x_q_send_update(struct bnx2x *bp, 
	/* Fill the ramrod data */

	bnx2x_q_fill_update_data(bp, o, update_params, rdata);



	/* No need for an explicit memory barrier here as long we would

	 * need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read and we will have to put a full memory barrier there

	 * (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */



	return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,

			     o->cids[cid_index], U64_HI(data_mapping),

			     U64_LO(data_mapping), ETH_CONNECTION_TYPE);
@@ -4813,11 +4809,62 @@ static inline int bnx2x_q_send_activate(struct bnx2x *bp, 
	return bnx2x_q_send_update(bp, params);

}



static void bnx2x_q_fill_update_tpa_data(struct bnx2x *bp,

				struct bnx2x_queue_sp_obj *obj,

				struct bnx2x_queue_update_tpa_params *params,

				struct tpa_update_ramrod_data *data)

{

	data->client_id = obj->cl_id;

	data->complete_on_both_clients = params->complete_on_both_clients;

	data->dont_verify_rings_pause_thr_flg =

		params->dont_verify_thr;

	data->max_agg_size = cpu_to_le16(params->max_agg_sz);

	data->max_sges_for_packet = params->max_sges_pkt;

	data->max_tpa_queues = params->max_tpa_queues;

	data->sge_buff_size = cpu_to_le16(params->sge_buff_sz);

	data->sge_page_base_hi = cpu_to_le32(U64_HI(params->sge_map));

	data->sge_page_base_lo = cpu_to_le32(U64_LO(params->sge_map));

	data->sge_pause_thr_high = cpu_to_le16(params->sge_pause_thr_high);

	data->sge_pause_thr_low = cpu_to_le16(params->sge_pause_thr_low);

	data->tpa_mode = params->tpa_mode;

	data->update_ipv4 = params->update_ipv4;

	data->update_ipv6 = params->update_ipv6;

}



static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp,

					struct bnx2x_queue_state_params *params)

{

	/* TODO: Not implemented yet. */

	return -1;

	struct bnx2x_queue_sp_obj *o = params->q_obj;

	struct tpa_update_ramrod_data *rdata =

		(struct tpa_update_ramrod_data *)o->rdata;

	dma_addr_t data_mapping = o->rdata_mapping;

	struct bnx2x_queue_update_tpa_params *update_tpa_params =

		&params->params.update_tpa;

	u16 type;



	/* Clear the ramrod data */

	memset(rdata, 0, sizeof(*rdata));



	/* Fill the ramrod data */

	bnx2x_q_fill_update_tpa_data(bp, o, update_tpa_params, rdata);



	/* Add the function id inside the type, so that sp post function

	 * doesn't automatically add the PF func-id, this is required

	 * for operations done by PFs on behalf of their VFs

	 */

	type = ETH_CONNECTION_TYPE |

		((o->func_id) << SPE_HDR_FUNCTION_ID_SHIFT);



	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */

	return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TPA_UPDATE,

			     o->cids[BNX2X_PRIMARY_CID_INDEX],

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), type);

}



static inline int bnx2x_q_send_halt(struct bnx2x *bp,
@@ -5647,6 +5694,12 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp, 
	rdata->tx_switch_suspend = switch_update_params->suspend;

	rdata->echo = SWITCH_UPDATE;



	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */

	return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), NONE_CONNECTION_TYPE);
@@ -5674,11 +5727,11 @@ static inline int bnx2x_func_send_afex_update(struct bnx2x *bp, 
	rdata->allowed_priorities = afex_update_params->allowed_priorities;

	rdata->echo = AFEX_UPDATE;



	/*  No need for an explicit memory barrier here as long we would

	 *  need to ensure the ordering of writing to the SPQ element

	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 *  read and we will have to put a full memory barrier there

	 *  (inside bnx2x_sp_post()).

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */

	DP(BNX2X_MSG_SP,

	   "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
@@ -5763,6 +5816,12 @@ static inline int bnx2x_func_send_tx_start(struct bnx2x *bp, 
		rdata->traffic_type_to_priority_cos[i] =

			tx_start_params->traffic_type_to_priority_cos[i];



	/* No need for an explicit memory barrier here as long as we

	 * ensure the ordering of writing to the SPQ element

	 * and updating of the SPQ producer which involves a memory

	 * read. If the memory read is removed we will have to put a

	 * full memory barrier there (inside bnx2x_sp_post()).

	 */

	return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,

			     U64_HI(data_mapping),

			     U64_LO(data_mapping), NONE_CONNECTION_TYPE);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h

+19 −0
Original line number Diff line number Diff line
@@ -893,6 +893,24 @@ struct bnx2x_queue_update_params { 
	u8		cid_index;

};



struct bnx2x_queue_update_tpa_params {

	dma_addr_t sge_map;

	u8 update_ipv4;

	u8 update_ipv6;

	u8 max_tpa_queues;

	u8 max_sges_pkt;

	u8 complete_on_both_clients;

	u8 dont_verify_thr;

	u8 tpa_mode;

	u8 _pad;



	u16 sge_buff_sz;

	u16 max_agg_sz;



	u16 sge_pause_thr_low;

	u16 sge_pause_thr_high;

};



struct rxq_pause_params {

	u16		bd_th_lo;

	u16		bd_th_hi;
@@ -987,6 +1005,7 @@ struct bnx2x_queue_state_params { 
	/* Params according to the current command */

	union {

		struct bnx2x_queue_update_params	update;

		struct bnx2x_queue_update_tpa_params    update_tpa;

		struct bnx2x_queue_setup_params		setup;

		struct bnx2x_queue_init_params		init;

		struct bnx2x_queue_setup_tx_only_params	tx_only;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c

+82 −0
Original line number Diff line number Diff line
@@ -176,6 +176,11 @@ enum bnx2x_vfop_rss_state { 
	   BNX2X_VFOP_RSS_DONE

};



enum bnx2x_vfop_tpa_state {

	   BNX2X_VFOP_TPA_CONFIG,

	   BNX2X_VFOP_TPA_DONE

};



#define bnx2x_vfop_reset_wq(vf)	atomic_set(&vf->op_in_progress, 0)



void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
@@ -3047,6 +3052,83 @@ int bnx2x_vfop_rss_cmd(struct bnx2x *bp, 
	return -ENOMEM;

}



/* VFOP tpa update, send update on all queues */

static void bnx2x_vfop_tpa(struct bnx2x *bp, struct bnx2x_virtf *vf)

{

	struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);

	struct bnx2x_vfop_args_tpa *tpa_args = &vfop->args.tpa;

	enum bnx2x_vfop_tpa_state state = vfop->state;



	bnx2x_vfop_reset_wq(vf);



	if (vfop->rc < 0)

		goto op_err;



	DP(BNX2X_MSG_IOV, "vf[%d:%d] STATE: %d\n",

	   vf->abs_vfid, tpa_args->qid,

	   state);



	switch (state) {

	case BNX2X_VFOP_TPA_CONFIG:



		if (tpa_args->qid < vf_rxq_count(vf)) {

			struct bnx2x_queue_state_params *qstate =

				&vf->op_params.qstate;



			qstate->q_obj = &bnx2x_vfq(vf, tpa_args->qid, sp_obj);



			/* The only thing that changes for the ramrod params

			 * between calls is the sge_map

			 */

			qstate->params.update_tpa.sge_map =

				tpa_args->sge_map[tpa_args->qid];



			DP(BNX2X_MSG_IOV, "sge_addr[%d] %08x:%08x\n",

			   tpa_args->qid,

			   U64_HI(qstate->params.update_tpa.sge_map),

			   U64_LO(qstate->params.update_tpa.sge_map));

			qstate->cmd = BNX2X_Q_CMD_UPDATE_TPA;

			vfop->rc = bnx2x_queue_state_change(bp, qstate);



			tpa_args->qid++;

			bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);

		}

		vfop->state = BNX2X_VFOP_TPA_DONE;

		vfop->rc = 0;

		bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);

op_err:

		BNX2X_ERR("TPA update error: rc %d\n", vfop->rc);

op_done:

	case BNX2X_VFOP_TPA_DONE:

		bnx2x_vfop_end(bp, vf, vfop);

		return;

	default:

		bnx2x_vfop_default(state);

	}

op_pending:

	return;

}



int bnx2x_vfop_tpa_cmd(struct bnx2x *bp,

			struct bnx2x_virtf *vf,

			struct bnx2x_vfop_cmd *cmd,

			struct vfpf_tpa_tlv *tpa_tlv)

{

	struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);



	if (vfop) {

		vfop->args.qx.qid = 0; /* loop */

		memcpy(&vfop->args.tpa.sge_map,

		       tpa_tlv->tpa_client_info.sge_addr,

		       sizeof(vfop->args.tpa.sge_map));

		bnx2x_vfop_opset(BNX2X_VFOP_TPA_CONFIG,

				 bnx2x_vfop_tpa, cmd->done);

		return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_tpa,

					     cmd->block);

	}

	return -ENOMEM;

}



/* VF release ~ VF close + VF release-resources

 * Release is the ultimate SW shutdown and is called whenever an

 * irrecoverable error is encountered.