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Commit 14a13a0e authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher
Browse files

drm/amd/display: Remove COMBO_DISPLAY_PLL0 from Vega20 



Signed-off-by: default avatarJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
parent 138bc360

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+10 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
#endif

#include "core_types.h"

#include "dc_types.h"



#include "dal_asic_id.h"



#define TO_DCE_CLOCKS(clocks)\

	container_of(clocks, struct dce_disp_clk, base)
@@ -413,9 +413,18 @@ static int dce112_set_clock( 
	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/

	dce_clk_params.target_clock_frequency = 0;

	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;

#ifndef CONFIG_DRM_AMD_DC_VG20

	dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =

			(dce_clk_params.pll_id ==

					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);

#else

	if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev))

		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =

			(dce_clk_params.pll_id ==

					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);

	else

		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;

#endif



	bp->funcs->set_dce_clock(bp, &dce_clk_params);

drivers/gpu/drm/amd/display/include/dal_asic_id.h

+6 −0
Original line number Diff line number Diff line
@@ -117,6 +117,12 @@ 
	((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))



/* DCE12 */

#define AI_UNKNOWN 0xFF



#ifdef CONFIG_DRM_AMD_DC_VG20

#define AI_VEGA20_P_A0 40

#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))

#endif



#define AI_GREENLAND_P_A0 1

#define AI_GREENLAND_P_A1 2