Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 14321604 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v4.18' of... 

Merge tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

Renesas ARM Based SoC DT Updates for v4.18

* R-Mobile A1 (r8a7740) SoC
  - Describe CEU, IRQC, SYS-DMAC and USB devices
  - Cleanup for consistency with other Renesas SoCs and enhanced maintainability
* RZ/A1H (r7s72100) SoC
  - Describe CEU device
* R-Car Gen2, RZ/G1 and RZ/A1H SoCs
  - Add PMU device nodes
* RZ/A1H (r7s72100) SoC
  - Correct interrupt types
* R-Mobile APE6 (r8a73a4) APE4EVM board and SH-Mobile AG5 (sh73a0) SoC
  - Use generic disable-wp instead of now deprecated
    toshiba,mmc-wrprotect-disable property
* EMMA Mobile EV2 (emev2) and SH-Mobile AG5 (sh73a0) SoCs
  - Add missing interrupt-affinity to PMU
* R-Car H2 (r8a7790) and R-Mobile APE6 (r8a73a4) SoCs
  - Correct mask for GIC PPI interrupts
* R-Car H2 (r8a7790), M2-W (r8a7791), M2-N (r8a7793) and E2 (r8a7794) SoCs
  - Describe FDP1 instances
* R-Car Gen2 and RZ/G1 SoCs
  - Describe watchdog devices
  - For R-Car Gen2 this involves updating the SMP routine side as
    it is changed by a driver updated to allow watchdog device support

* Alt board for R-Car E2 (r8a7794) SoC
* RBoards for -Car Gen2 SoCs and kzm9d board for EMMA Mobile EV2 (emev2) SoC
* iW-RainboW-G23S board for RZ/G1C (r8a77470) SoC
  - Initial SoC and board support
  - Enable EtherAVB
  - Describe all SCIF devices
* Boards for R-Car Gen2 SoCs
  - Enable watchdog support
* Wheat board for V2H (r8a7792) SoC
  - Correct ADV7513 address usage

* tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (69 commits)
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  ARM: dts: r8a7745: Add PMU device node
  ARM: dts: r8a7743: Add PMU device node
  ARM: dts: r8a7794: Add PMU device node
  ARM: dts: r8a7793: Add PMU device node
  ARM: dts: r8a7792: Add PMU device node
  ARM: dts: r8a7791: Add PMU device node
  ARM: dts: r8a7790: Add PMU device nodes
  ARM: dts: r7s72100: Add PMU device node
  ARM: dts: r7s72100: Correct RTC interrupt types
  ARM: dts: r7s72100: Correct watchdog timer interrupt type
  ARM: dts: emev2: Add missing interrupt-affinity to PMU node
  ARM: dts: sh73a0: Add missing interrupt-affinity to PMU node
  ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
  ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
  ARM: shmobile: r8a7794: alt: add EEPROM to DTS
  ARM: dts: kzm9d: Drop unnecessary address properties from gpio_keys node
  ARM: dts: silk: Drop unnecessary address properties from vin port node
  ARM: dts: alt: Drop unnecessary address properties from vin port node
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 171d429a 7fad92d0

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -795,6 +795,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ 
	r8a7745-iwg22d-sodimm.dtb \

	r8a7745-iwg22d-sodimm-dbhd-ca.dtb \

	r8a7745-sk-rzg1e.dtb \

	r8a77470-iwg23s-sbc.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen.dtb \

	r8a7790-lager.dtb \

arch/arm/boot/dts/emev2-kzm9d.dts

+0 −3
Original line number Diff line number Diff line
@@ -34,9 +34,6 @@ 


	gpio_keys {

		compatible = "gpio-keys";

		#address-cells = <1>;

		#size-cells = <0>;



		one {

			debounce-interval = <50>;

			wakeup-source;

arch/arm/boot/dts/emev2.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -31,13 +31,13 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			clock-frequency = <533000000>;

		};

		cpu@1 {

		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;
@@ -57,6 +57,7 @@ 
		compatible = "arm,cortex-a9-pmu";

		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>, <&cpu1>;

	};



	clocks@e0110000 {

arch/arm/boot/dts/r7s72100.dtsi

+538 −500
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 


/ {

	compatible = "renesas,r7s72100";

	interrupt-parent = <&gic>;

	#address-cells = <1>;

	#size-cells = <1>;
@@ -31,40 +30,6 @@ 
		spi4 = &spi4;

	};



	clocks {

		ranges;

		#address-cells = <1>;

		#size-cells = <1>;



		/* External clocks */

		extal_clk: extal {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

		};



		usb_x1_clk: usb_x1 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

		};



		rtc_x1_clk: rtc_x1 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board to 32678 */

			clock-frequency = <0>;

		};



		rtc_x3_clk: rtc_x3 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board to 4000000 */

			clock-frequency = <0>;

		};



	/* Fixed factor clocks */

	b_clk: b {

		#clock-cells = <0>;
@@ -73,126 +38,6 @@ 
		clock-mult = <1>;

		clock-div = <3>;

	};

		p1_clk: p1 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <6>;

		};

		p0_clk: p0 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <12>;

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@fcfe0000 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-cpg-clocks",

				     "renesas,rz-cpg-clocks";

			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

			#power-domain-cells = <0>;

		};



		/* MSTP clocks */

		mstp3_clks: mstp3_clks@fcfe0420 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0420 4>;

			clocks = <&p0_clk>;

			clock-indices = <R7S72100_CLK_MTU2>;

			clock-output-names = "mtu2";

		};



		mstp4_clks: mstp4_clks@fcfe0424 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0424 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,

				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3

				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7

			>;

			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";

		};



		mstp5_clks: mstp5_clks@fcfe0428 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0428 4>;

			clocks = <&p0_clk>, <&p0_clk>;

			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;

			clock-output-names = "ostm0", "ostm1";

		};



		mstp6_clks: mstp6_clks@fcfe042c {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe042c 4>;

			clocks = <&p0_clk>;

			clock-indices = <R7S72100_CLK_RTC>;

			clock-output-names = "rtc";

		};



		mstp7_clks: mstp7_clks@fcfe0430 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0430 4>;

			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;

			clock-output-names = "ether", "usb0", "usb1";

		};



		mstp8_clks: mstp8_clks@fcfe0434 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0434 4>;

			clocks = <&p1_clk>;

			clock-indices = <R7S72100_CLK_MMCIF>;

			clock-output-names = "mmcif";

		};



		mstp9_clks: mstp9_clks@fcfe0438 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0438 4>;

			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;

			clock-indices = <

				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3

			>;

			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";

		};



		mstp10_clks: mstp10_clks@fcfe043c {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe043c 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,

				 <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3

				R7S72100_CLK_SPI4

			>;

			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";

		};

		mstp12_clks: mstp12_clks@fcfe0444 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0444 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01

				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11

			>;

			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";

		};

	};



	cpus {

		#address-cells = <1>;
@@ -208,82 +53,65 @@ 
		};

	};



	pinctrl: pin-controller@fcfe3000 {

		compatible = "renesas,r7s72100-ports";



		reg = <0xfcfe3000 0x4230>;



		port0: gpio-0 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 0 6>;

		};



		port1: gpio-1 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 16 16>;

		};



		port2: gpio-2 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 32 16>;

		};



		port3: gpio-3 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 48 16>;

	/* External clocks */

	extal_clk: extal {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		/* If clk present, value must be set by board */

		clock-frequency = <0>;

	};



		port4: gpio-4 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 64 16>;

	p0_clk: p0 {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&cpg_clocks R7S72100_CLK_PLL>;

		clock-mult = <1>;

		clock-div = <12>;

	};



		port5: gpio-5 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 80 11>;

	p1_clk: p1 {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&cpg_clocks R7S72100_CLK_PLL>;

		clock-mult = <1>;

		clock-div = <6>;

	};



		port6: gpio-6 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 96 16>;

	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;

	};



		port7: gpio-7 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 112 16>;

	rtc_x1_clk: rtc_x1 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		/* If clk present, value must be set by board to 32678 */

		clock-frequency = <0>;

	};



		port8: gpio-8 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 128 16>;

	rtc_x3_clk: rtc_x3 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		/* If clk present, value must be set by board to 4000000 */

		clock-frequency = <0>;

	};



		port9: gpio-9 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 144 8>;

		};

	soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;



		port10: gpio-10 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 160 16>;

		};

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		port11: gpio-11 {

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pinctrl 0 176 16>;

		};

		L2: cache-controller@3ffff000 {

			compatible = "arm,pl310-cache";

			reg = <0x3ffff000 0x1000>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

			arm,early-bresp-disable;

			arm,full-line-zero-disable;

			cache-unified;

			cache-level = <2>;

		};



		scif0: serial@e8007000 {
@@ -465,8 +293,73 @@ 
			status = "disabled";

		};



	gic: interrupt-controller@e8201000 {

		compatible = "arm,pl390";

		usbhs0: usb@e8010000 {

			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";

			reg = <0xe8010000 0x1a0>;

			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R7S72100_CLK_USB0>;

			renesas,buswait = <4>;

			power-domains = <&cpg_clocks>;

			status = "disabled";

		};



		usbhs1: usb@e8207000 {

			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";

			reg = <0xe8207000 0x1a0>;

			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R7S72100_CLK_USB1>;

			renesas,buswait = <4>;

			power-domains = <&cpg_clocks>;

			status = "disabled";

		};



		mmcif: mmc@e804c800 {

			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";

			reg = <0xe804c800 0x80>;

			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;

			power-domains = <&cpg_clocks>;

			reg-io-width = <4>;

			bus-width = <8>;

			status = "disabled";

		};



		sdhi0: sd@e804e000 {

			compatible = "renesas,sdhi-r7s72100";

			reg = <0xe804e000 0x100>;

			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,

				 <&mstp12_clks R7S72100_CLK_SDHI01>;

			clock-names = "core", "cd";

			power-domains = <&cpg_clocks>;

			cap-sd-highspeed;

			cap-sdio-irq;

			status = "disabled";

		};



		sdhi1: sd@e804e800 {

			compatible = "renesas,sdhi-r7s72100";

			reg = <0xe804e800 0x100>;

			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,

				 <&mstp12_clks R7S72100_CLK_SDHI11>;

			clock-names = "core", "cd";

			power-domains = <&cpg_clocks>;

			cap-sd-highspeed;

			cap-sdio-irq;

			status = "disabled";

		};



		gic: interrupt-controller@e8201000 {

			compatible = "arm,pl390";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;
@@ -474,21 +367,234 @@ 
				<0xe8202000 0x1000>;

		};



	L2: cache-controller@3ffff000 {

		compatible = "arm,pl310-cache";

		reg = <0x3ffff000 0x1000>;

		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

		arm,early-bresp-disable;

		arm,full-line-zero-disable;

		cache-unified;

		cache-level = <2>;

		ether: ethernet@e8203000 {

			compatible = "renesas,ether-r7s72100";

			reg = <0xe8203000 0x800>,

			      <0xe8204800 0x200>;

			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;

			power-domains = <&cpg_clocks>;

			phy-mode = "mii";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		ceu: camera@e8210000 {

			reg = <0xe8210000 0x3000>;

			compatible = "renesas,r7s72100-ceu";

			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp6_clks R7S72100_CLK_CEU>;

			power-domains = <&cpg_clocks>;

			status = "disabled";

		};



		wdt: watchdog@fcfe0000 {

			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";

			reg = <0xfcfe0000 0x6>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;

			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&p0_clk>;

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@fcfe0000 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-cpg-clocks",

				     "renesas,rz-cpg-clocks";

			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

			#power-domain-cells = <0>;

		};



		/* MSTP clocks */

		mstp3_clks: mstp3_clks@fcfe0420 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0420 4>;

			clocks = <&p0_clk>;

			clock-indices = <R7S72100_CLK_MTU2>;

			clock-output-names = "mtu2";

		};



		mstp4_clks: mstp4_clks@fcfe0424 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0424 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,

				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3

				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7

			>;

			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";

		};



		mstp5_clks: mstp5_clks@fcfe0428 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0428 4>;

			clocks = <&p0_clk>, <&p0_clk>;

			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;

			clock-output-names = "ostm0", "ostm1";

		};



		mstp6_clks: mstp6_clks@fcfe042c {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe042c 4>;

			clocks = <&b_clk>, <&p0_clk>;

			clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;

			clock-output-names = "ceu", "rtc";

		};



		mstp7_clks: mstp7_clks@fcfe0430 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0430 4>;

			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;

			clock-output-names = "ether", "usb0", "usb1";

		};



		mstp8_clks: mstp8_clks@fcfe0434 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0434 4>;

			clocks = <&p1_clk>;

			clock-indices = <R7S72100_CLK_MMCIF>;

			clock-output-names = "mmcif";

		};



		mstp9_clks: mstp9_clks@fcfe0438 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0438 4>;

			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;

			clock-indices = <

				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3

			>;

			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";

		};



		mstp10_clks: mstp10_clks@fcfe043c {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe043c 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,

				 <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3

				R7S72100_CLK_SPI4

			>;

			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";

		};

		mstp12_clks: mstp12_clks@fcfe0444 {

			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0444 4>;

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01

				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11

			>;

			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";

		};



		pinctrl: pin-controller@fcfe3000 {

			compatible = "renesas,r7s72100-ports";



			reg = <0xfcfe3000 0x4230>;



			port0: gpio-0 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 0 6>;

			};



			port1: gpio-1 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 16 16>;

			};



			port2: gpio-2 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 32 16>;

			};



			port3: gpio-3 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 48 16>;

			};



			port4: gpio-4 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 64 16>;

			};



			port5: gpio-5 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 80 11>;

			};



			port6: gpio-6 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 96 16>;

			};



			port7: gpio-7 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 112 16>;

			};



			port8: gpio-8 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 128 16>;

			};



			port9: gpio-9 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 144 8>;

			};



			port10: gpio-10 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 160 16>;

			};



			port11: gpio-11 {

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl 0 176 16>;

			};

		};



		ostm0: timer@fcfec000 {

			compatible = "renesas,r7s72100-ostm", "renesas,ostm";

			reg = <0xfcfec000 0x30>;

			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;

			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;

			power-domains = <&cpg_clocks>;

			status = "disabled";

		};



		ostm1: timer@fcfec400 {

			compatible = "renesas,r7s72100-ostm", "renesas,ostm";

			reg = <0xfcfec400 0x30>;

			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;

			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;

			power-domains = <&cpg_clocks>;

			status = "disabled";

		};



		i2c0: i2c@fcfee000 {
@@ -578,88 +684,12 @@ 
			status = "disabled";

		};



	ether: ethernet@e8203000 {

		compatible = "renesas,ether-r7s72100";

		reg = <0xe8203000 0x800>,

		      <0xe8204800 0x200>;

		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp7_clks R7S72100_CLK_ETHER>;

		power-domains = <&cpg_clocks>;

		phy-mode = "mii";

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";

	};



	mmcif: mmc@e804c800 {

		compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";

		reg = <0xe804c800 0x80>;

		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;

		power-domains = <&cpg_clocks>;

		reg-io-width = <4>;

		bus-width = <8>;

		status = "disabled";

	};



	sdhi0: sd@e804e000 {

		compatible = "renesas,sdhi-r7s72100";

		reg = <0xe804e000 0x100>;

		interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,

			 <&mstp12_clks R7S72100_CLK_SDHI01>;

		clock-names = "core", "cd";

		power-domains = <&cpg_clocks>;

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";

	};



	sdhi1: sd@e804e800 {

		compatible = "renesas,sdhi-r7s72100";

		reg = <0xe804e800 0x100>;

		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,

			 <&mstp12_clks R7S72100_CLK_SDHI11>;

		clock-names = "core", "cd";

		power-domains = <&cpg_clocks>;

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";

	};



	ostm0: timer@fcfec000 {

		compatible = "renesas,r7s72100-ostm", "renesas,ostm";

		reg = <0xfcfec000 0x30>;

		interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;

		clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



	ostm1: timer@fcfec400 {

		compatible = "renesas,r7s72100-ostm", "renesas,ostm";

		reg = <0xfcfec400 0x30>;

		interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;

		clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};



		rtc: rtc@fcff1000 {

			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";

			reg = <0xfcff1000 0x2e>;

		interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING

			      GIC_SPI 277 IRQ_TYPE_EDGE_RISING

			      GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;

			interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "alarm", "period", "carry";

			clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,

				 <&rtc_x3_clk>, <&extal_clk>;
@@ -668,3 +698,11 @@ 
			status = "disabled";

		};

	};



	usb_x1_clk: usb_x1 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		/* If clk present, value must be set by board */

		clock-frequency = <0>;

	};

};

arch/arm/boot/dts/r8a73a4-ape6evm.dts

+2 −2
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ 
&sdhi0 {

	vmmc-supply = <&vcc_sdhi0>;

	bus-width = <4>;

	toshiba,mmc-wrprotect-disable;

	disable-wp;

	pinctrl-names = "default";

	pinctrl-0 = <&sdhi0_pins>;

	status = "okay";
@@ -244,7 +244,7 @@ 
	vmmc-supply = <&ape6evm_fixed_3v3>;

	bus-width = <4>;

	broken-cd;

	toshiba,mmc-wrprotect-disable;

	disable-wp;

	pinctrl-names = "default";

	pinctrl-0 = <&sdhi1_pins>;

	status = "okay";