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Commit 139787f4 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
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arm64: dts: berlin4ct: Add L2 cache topology 



This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.

[Sebastian: rename cache node from "l2-cache" to "cache"]

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 7091eb96

arch/arm64/boot/dts/marvell/berlin4ct.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ 
			device_type = "cpu";

			reg = <0x0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_SLEEP_0>;

		};
@@ -76,6 +77,7 @@ 
			device_type = "cpu";

			reg = <0x1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_SLEEP_0>;

		};
@@ -84,6 +86,7 @@ 
			device_type = "cpu";

			reg = <0x2>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_SLEEP_0>;

		};
@@ -92,9 +95,14 @@ 
			device_type = "cpu";

			reg = <0x3>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_SLEEP_0>;

		};



		l2: cache {

			compatible = "cache";

		};



		idle-states {

			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {