Loading drivers/clk/qcom/Kconfig +9 −0 Original line number Diff line number Diff line Loading @@ -624,3 +624,12 @@ config SM_GPUCC_KHAJE Support for the graphics clock controller on Qualcomm Technologies, Inc KHAJE devices. Say Y if you want to support graphics controller devices. config SM_DISPCC_KHAJE tristate "KHAJE Display Clock Controller" select SM_GCC_KHAJE help Support for the display clock controller on Qualcomm Technologies, Inc. KHAJE devices. Say Y if you want to support display devices and functionality such as splash screen. drivers/clk/qcom/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -74,6 +74,7 @@ obj-$(CONFIG_SM_CAMCC_LITO) += camcc-lito.o obj-$(CONFIG_SM_DEBUGCC_BENGAL) += debugcc-bengal.o obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o obj-$(CONFIG_SM_DISPCC_BENGAL) += dispcc-bengal.o obj-$(CONFIG_SM_DISPCC_KHAJE) += dispcc-khaje.o obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o obj-$(CONFIG_SM_GCC_KHAJE) += gcc-khaje.o Loading drivers/clk/qcom/dispcc-khaje.c 0 → 100644 +637 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,dispcc-khaje.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "clk-regmap.h" #include "common.h" #include "vdd-level-bengal.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner); enum { P_BI_TCXO, P_DISP_CC_PLL0_OUT_EVEN, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_GCC_DISP_GPLL0_DIV_CLK_SRC, }; static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, }; static const char * const disp_cc_parent_names_0[] = { "bi_tcxo", "dsi0_phy_pll_out_byteclk", }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 }, { P_DISP_CC_PLL0_OUT_EVEN, 5 }, }; static const char * const disp_cc_parent_names_1[] = { "bi_tcxo", "disp_cc_pll0", "gcc_disp_gpll0_div_clk_src", "disp_cc_pll0", }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 }, }; static const char * const disp_cc_parent_names_2[] = { "bi_tcxo", "gcc_disp_gpll0_div_clk_src", }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, }; static const char * const disp_cc_parent_names_3[] = { "bi_tcxo", "dsi0_phy_pll_out_dsiclk", }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, }; static const char * const disp_cc_parent_names_4[] = { "bi_tcxo", }; static struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; /* 615MHz configuration */ static const struct alpha_pll_config disp_cc_pll0_config = { .l = 0x20, .alpha = 0x800, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002261, .config_ctl_hi1_val = 0x329A299C, .user_ctl_val = 0x00000001, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x00000000, }; static struct clk_alpha_pll disp_cc_pll0 = { .offset = 0x0, .vco_table = lucid_vco, .num_vco = ARRAY_SIZE(lucid_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_pll0", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1500000000, [VDD_NOMINAL] = 1750000000, [VDD_HIGH] = 2000000000}, }, }, }; static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .reg = 0x10dc, .shift = 0, .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_clk_src" }, .num_parents = 1, .ops = &clk_regmap_div_ops, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 8, 0, 0), F(75000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .cmd_rcgr = 0x115c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_names = disp_cc_parent_names_2, .num_parents = ARRAY_SIZE(disp_cc_parent_names_2), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000, [VDD_LOW] = 37500000, [VDD_NOMINAL] = 75000000}, }, }; static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .cmd_rcgr = 0x10c4, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_names = disp_cc_parent_names_0, .num_parents = ARRAY_SIZE(disp_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 187500000, [VDD_LOW] = 300000000, [VDD_LOW_L1] = 358000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .cmd_rcgr = 0x10e0, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_names = disp_cc_parent_names_0, .num_parents = ARRAY_SIZE(disp_cc_parent_names_0), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0), F(383000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .cmd_rcgr = 0x107c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_names = disp_cc_parent_names_1, .num_parents = ARRAY_SIZE(disp_cc_parent_names_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000, [VDD_LOW_L1] = 383000000, [VDD_NOMINAL] = 470000000, [VDD_HIGH] = 560000000}, }, }; static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .cmd_rcgr = 0x1064, .mnd_width = 8, .hid_width = 5, .parent_map = disp_cc_parent_map_3, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_names = disp_cc_parent_names_3, .num_parents = ARRAY_SIZE(disp_cc_parent_names_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 525000000, [VDD_LOW_L1] = 625000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .cmd_rcgr = 0x1094, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_names = disp_cc_parent_names_1, .num_parents = ARRAY_SIZE(disp_cc_parent_names_1), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000}, }, }; static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .cmd_rcgr = 0x10ac, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_names = disp_cc_parent_names_4, .num_parents = ARRAY_SIZE(disp_cc_parent_names_4), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static struct clk_branch disp_cc_mdss_ahb_clk = { .halt_reg = 0x104c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x104c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_clk = { .halt_reg = 0x102c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x102c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .halt_reg = 0x1030, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1030, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_div_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg = 0x1034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_esc0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_clk = { .halt_reg = 0x1010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", .parent_names = (const char *[]){ "disp_cc_mdss_mdp_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .halt_reg = 0x1020, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x1020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", .parent_names = (const char *[]){ "disp_cc_mdss_mdp_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .halt_reg = 0x2004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x2004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_pclk0_clk = { .halt_reg = 0x1168, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1168, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_pclk0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rot_clk = { .halt_reg = 0x1018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", .parent_names = (const char *[]){ "disp_cc_mdss_rot_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { .halt_reg = 0x200c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x200c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .halt_reg = 0x2008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", .parent_names = (const char *[]){ "disp_cc_mdss_vsync_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_vsync_clk = { .halt_reg = 0x1028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", .parent_names = (const char *[]){ "disp_cc_mdss_vsync_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *disp_cc_khaje_clocks[] = { [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, [DISP_CC_PLL0] = &disp_cc_pll0.clkr, }; static const struct regmap_config disp_cc_khaje_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x10000, .fast_io = true, }; static const struct qcom_cc_desc disp_cc_khaje_desc = { .config = &disp_cc_khaje_regmap_config, .clks = disp_cc_khaje_clocks, .num_clks = ARRAY_SIZE(disp_cc_khaje_clocks), }; static const struct of_device_id disp_cc_khaje_match_table[] = { { .compatible = "qcom,khaje-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_khaje_match_table); static int disp_cc_khaje_probe(struct platform_device *pdev) { struct regmap *regmap; struct clk *clk; int ret; vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); if (IS_ERR(vdd_cx.regulator[0])) { if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); return PTR_ERR(vdd_cx.regulator[0]); } clk = clk_get(&pdev->dev, "cfg_ahb_clk"); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); return PTR_ERR(clk); } clk_put(clk); regmap = qcom_cc_map(pdev, &disp_cc_khaje_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); /* * Keep the clock always-ON * DISP_CC_SLEEP_CLK, DISP_CC_XO_CLK */ regmap_update_bits(regmap, 0x5004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); ret = qcom_cc_really_probe(pdev, &disp_cc_khaje_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered DISP CC clocks\n"); return ret; } static struct platform_driver disp_cc_khaje_driver = { .probe = disp_cc_khaje_probe, .driver = { .name = "disp_cc-khaje", .of_match_table = disp_cc_khaje_match_table, }, }; static int __init disp_cc_khaje_init(void) { return platform_driver_register(&disp_cc_khaje_driver); } subsys_initcall(disp_cc_khaje_init); static void __exit disp_cc_khaje_exit(void) { platform_driver_unregister(&disp_cc_khaje_driver); } module_exit(disp_cc_khaje_exit); MODULE_DESCRIPTION("QTI DISP_CC KHAJE Driver"); Loading
drivers/clk/qcom/Kconfig +9 −0 Original line number Diff line number Diff line Loading @@ -624,3 +624,12 @@ config SM_GPUCC_KHAJE Support for the graphics clock controller on Qualcomm Technologies, Inc KHAJE devices. Say Y if you want to support graphics controller devices. config SM_DISPCC_KHAJE tristate "KHAJE Display Clock Controller" select SM_GCC_KHAJE help Support for the display clock controller on Qualcomm Technologies, Inc. KHAJE devices. Say Y if you want to support display devices and functionality such as splash screen.
drivers/clk/qcom/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -74,6 +74,7 @@ obj-$(CONFIG_SM_CAMCC_LITO) += camcc-lito.o obj-$(CONFIG_SM_DEBUGCC_BENGAL) += debugcc-bengal.o obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o obj-$(CONFIG_SM_DISPCC_BENGAL) += dispcc-bengal.o obj-$(CONFIG_SM_DISPCC_KHAJE) += dispcc-khaje.o obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o obj-$(CONFIG_SM_GCC_KHAJE) += gcc-khaje.o Loading
drivers/clk/qcom/dispcc-khaje.c 0 → 100644 +637 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,dispcc-khaje.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "clk-regmap.h" #include "common.h" #include "vdd-level-bengal.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner); enum { P_BI_TCXO, P_DISP_CC_PLL0_OUT_EVEN, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_GCC_DISP_GPLL0_DIV_CLK_SRC, }; static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, }; static const char * const disp_cc_parent_names_0[] = { "bi_tcxo", "dsi0_phy_pll_out_byteclk", }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 }, { P_DISP_CC_PLL0_OUT_EVEN, 5 }, }; static const char * const disp_cc_parent_names_1[] = { "bi_tcxo", "disp_cc_pll0", "gcc_disp_gpll0_div_clk_src", "disp_cc_pll0", }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 }, }; static const char * const disp_cc_parent_names_2[] = { "bi_tcxo", "gcc_disp_gpll0_div_clk_src", }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, }; static const char * const disp_cc_parent_names_3[] = { "bi_tcxo", "dsi0_phy_pll_out_dsiclk", }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, }; static const char * const disp_cc_parent_names_4[] = { "bi_tcxo", }; static struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; /* 615MHz configuration */ static const struct alpha_pll_config disp_cc_pll0_config = { .l = 0x20, .alpha = 0x800, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002261, .config_ctl_hi1_val = 0x329A299C, .user_ctl_val = 0x00000001, .user_ctl_hi_val = 0x00000805, .user_ctl_hi1_val = 0x00000000, }; static struct clk_alpha_pll disp_cc_pll0 = { .offset = 0x0, .vco_table = lucid_vco, .num_vco = ARRAY_SIZE(lucid_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_pll0", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1500000000, [VDD_NOMINAL] = 1750000000, [VDD_HIGH] = 2000000000}, }, }, }; static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .reg = 0x10dc, .shift = 0, .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_clk_src" }, .num_parents = 1, .ops = &clk_regmap_div_ops, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 8, 0, 0), F(75000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .cmd_rcgr = 0x115c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_names = disp_cc_parent_names_2, .num_parents = ARRAY_SIZE(disp_cc_parent_names_2), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000, [VDD_LOW] = 37500000, [VDD_NOMINAL] = 75000000}, }, }; static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .cmd_rcgr = 0x10c4, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_names = disp_cc_parent_names_0, .num_parents = ARRAY_SIZE(disp_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 187500000, [VDD_LOW] = 300000000, [VDD_LOW_L1] = 358000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .cmd_rcgr = 0x10e0, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_names = disp_cc_parent_names_0, .num_parents = ARRAY_SIZE(disp_cc_parent_names_0), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0), F(383000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .cmd_rcgr = 0x107c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_names = disp_cc_parent_names_1, .num_parents = ARRAY_SIZE(disp_cc_parent_names_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000, [VDD_LOW_L1] = 383000000, [VDD_NOMINAL] = 470000000, [VDD_HIGH] = 560000000}, }, }; static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .cmd_rcgr = 0x1064, .mnd_width = 8, .hid_width = 5, .parent_map = disp_cc_parent_map_3, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_names = disp_cc_parent_names_3, .num_parents = ARRAY_SIZE(disp_cc_parent_names_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 525000000, [VDD_LOW_L1] = 625000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .cmd_rcgr = 0x1094, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_names = disp_cc_parent_names_1, .num_parents = ARRAY_SIZE(disp_cc_parent_names_1), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000}, }, }; static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .cmd_rcgr = 0x10ac, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_names = disp_cc_parent_names_4, .num_parents = ARRAY_SIZE(disp_cc_parent_names_4), .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static struct clk_branch disp_cc_mdss_ahb_clk = { .halt_reg = 0x104c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x104c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_clk = { .halt_reg = 0x102c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x102c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .halt_reg = 0x1030, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1030, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", .parent_names = (const char *[]){ "disp_cc_mdss_byte0_div_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg = 0x1034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_esc0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_clk = { .halt_reg = 0x1010, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", .parent_names = (const char *[]){ "disp_cc_mdss_mdp_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .halt_reg = 0x1020, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x1020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", .parent_names = (const char *[]){ "disp_cc_mdss_mdp_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .halt_reg = 0x2004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x2004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_pclk0_clk = { .halt_reg = 0x1168, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1168, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", .parent_names = (const char *[]){ "disp_cc_mdss_pclk0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rot_clk = { .halt_reg = 0x1018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", .parent_names = (const char *[]){ "disp_cc_mdss_rot_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { .halt_reg = 0x200c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x200c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_ahb_clk", .parent_names = (const char *[]){ "disp_cc_mdss_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .halt_reg = 0x2008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", .parent_names = (const char *[]){ "disp_cc_mdss_vsync_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_vsync_clk = { .halt_reg = 0x1028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", .parent_names = (const char *[]){ "disp_cc_mdss_vsync_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *disp_cc_khaje_clocks[] = { [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, [DISP_CC_PLL0] = &disp_cc_pll0.clkr, }; static const struct regmap_config disp_cc_khaje_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x10000, .fast_io = true, }; static const struct qcom_cc_desc disp_cc_khaje_desc = { .config = &disp_cc_khaje_regmap_config, .clks = disp_cc_khaje_clocks, .num_clks = ARRAY_SIZE(disp_cc_khaje_clocks), }; static const struct of_device_id disp_cc_khaje_match_table[] = { { .compatible = "qcom,khaje-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_khaje_match_table); static int disp_cc_khaje_probe(struct platform_device *pdev) { struct regmap *regmap; struct clk *clk; int ret; vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); if (IS_ERR(vdd_cx.regulator[0])) { if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); return PTR_ERR(vdd_cx.regulator[0]); } clk = clk_get(&pdev->dev, "cfg_ahb_clk"); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) dev_err(&pdev->dev, "Unable to get ahb clock handle\n"); return PTR_ERR(clk); } clk_put(clk); regmap = qcom_cc_map(pdev, &disp_cc_khaje_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); /* * Keep the clock always-ON * DISP_CC_SLEEP_CLK, DISP_CC_XO_CLK */ regmap_update_bits(regmap, 0x5004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); ret = qcom_cc_really_probe(pdev, &disp_cc_khaje_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered DISP CC clocks\n"); return ret; } static struct platform_driver disp_cc_khaje_driver = { .probe = disp_cc_khaje_probe, .driver = { .name = "disp_cc-khaje", .of_match_table = disp_cc_khaje_match_table, }, }; static int __init disp_cc_khaje_init(void) { return platform_driver_register(&disp_cc_khaje_driver); } subsys_initcall(disp_cc_khaje_init); static void __exit disp_cc_khaje_exit(void) { platform_driver_unregister(&disp_cc_khaje_driver); } module_exit(disp_cc_khaje_exit); MODULE_DESCRIPTION("QTI DISP_CC KHAJE Driver");
