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Commit 13174698 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add UBWC 4.0 support"

parents 2d3773e0 63f9e113

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+3 −0
Original line number Diff line number Diff line
@@ -100,12 +100,15 @@ enum { 
	SDE_HW_UBWC_VER_10 = SDE_HW_UBWC_VER(0x100),

	SDE_HW_UBWC_VER_20 = SDE_HW_UBWC_VER(0x200),

	SDE_HW_UBWC_VER_30 = SDE_HW_UBWC_VER(0x300),

	SDE_HW_UBWC_VER_40 = SDE_HW_UBWC_VER(0x400),

};



#define IS_UBWC_20_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_20)

#define IS_UBWC_30_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_30)

#define IS_UBWC_40_SUPPORTED(rev) \

		IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_UBWC_VER_40)



/**

 * Supported SSPP system cache settings

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+4 −1
Original line number Diff line number Diff line
@@ -332,7 +332,10 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
		SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,

			SDE_FETCH_CONFIG_RESET_VALUE |

			ctx->mdp->highest_bank_bit << 18);

		if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {

		if (IS_UBWC_40_SUPPORTED(ctx->catalog->ubwc_version)) {

			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

				SDE_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));

		} else if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) {

			alpha_en_mask = const_alpha_en ? BIT(31) : 0;

			SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,

				alpha_en_mask | (ctx->mdp->ubwc_swizzle) |

drivers/gpu/drm/msm/sde/sde_hw_top.c

+19 −1
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#define SSPP_SPARE                        0x28

#define UBWC_DEC_HW_VERSION               0x058

#define UBWC_STATIC                       0x144

#define UBWC_CTRL_2                       0x150

#define UBWC_PREDICTION_MODE              0x154



#define FLD_SPLIT_DISPLAY_CMD             BIT(1)

#define FLD_SMART_PANEL_FREE_RUN          BIT(2)
@@ -377,7 +379,23 @@ void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m) 
	c.blk_off = 0x0;

	ubwc_version = SDE_REG_READ(&c, UBWC_DEC_HW_VERSION);



	if (IS_UBWC_20_SUPPORTED(ubwc_version)) {

	if (IS_UBWC_40_SUPPORTED(ubwc_version)) {

		u32 ver = 2;

		u32 mode = 1;

		u32 reg = (m->mdp[0].ubwc_swizzle & 0x7) |

			((m->mdp[0].ubwc_static & 0x1) << 3) |

			((m->mdp[0].highest_bank_bit & 0x7) << 4) |

			((m->macrotile_mode & 0x1) << 12);



		if (IS_UBWC_30_SUPPORTED(m->ubwc_version)) {

			ver = 1;

			mode = 0;

		}



		SDE_REG_WRITE(&c, UBWC_STATIC, reg);

		SDE_REG_WRITE(&c, UBWC_CTRL_2, ver);

		SDE_REG_WRITE(&c, UBWC_PREDICTION_MODE, mode);

	} else if (IS_UBWC_20_SUPPORTED(ubwc_version)) {

		SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);

	} else if (IS_UBWC_30_SUPPORTED(ubwc_version)) {

		u32 reg = m->mdp[0].ubwc_static |