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Commit 1219715d authored by Ke Wei's avatar Ke Wei Committed by Lennert Buytenhek
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[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define 



Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.

This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.

Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
parent ab6d15d5

arch/arm/plat-orion/time.c

+3 −3
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) 
	/*

	 * Clear and enable clockevent timer interrupt.

	 */

	writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);

	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);



	u = readl(BRIDGE_MASK);

	u |= BRIDGE_INT_TIMER1;
@@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) 
		/*

		 * ACK pending timer interrupt.

		 */

		writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);

		writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);



	}

	local_irq_restore(flags);
@@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) 
	/*

	 * ACK timer interrupt and call event handler.

	 */

	writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);

	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);

	orion_clkevt.event_handler(&orion_clkevt);



	return IRQ_HANDLED;

include/asm-arm/arch-orion5x/orion5x.h

+1 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ 
#define BRIDGE_MASK		ORION5X_BRIDGE_REG(0x114)

#define  BRIDGE_INT_TIMER0	0x0002

#define  BRIDGE_INT_TIMER1	0x0004

#define  BRIDGE_INT_TIMER1_CLR	(~0x0004)

#define MAIN_IRQ_CAUSE		ORION5X_BRIDGE_REG(0x200)

#define MAIN_IRQ_MASK		ORION5X_BRIDGE_REG(0x204)