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Commit 1202b4c6 authored by Wu Fengguang's avatar Wu Fengguang Committed by Keith Packard
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drm/i915: rename audio ELD registers 



Change the definitions from GEN5 to IBX as they aren't in the CPU and
some SNB systems actually shipped with IBX chipsets (or, at least that's
a supported configuration).

The GEN7_* register addresses actually take effect since GEN6 and should
be prefixed by CPT, the PCH code name.

Suggested-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarWu Fengguang <fengguang.wu@intel.com>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent b3f33cbf

drivers/gpu/drm/i915/i915_reg.h

+12 −12
Original line number Diff line number Diff line
@@ -3569,17 +3569,17 @@ 
#define G4X_ELD_ACK			(1 << 4)

#define G4X_HDMIW_HDMIEDID		0x6210C



#define GEN5_HDMIW_HDMIEDID_A		0xE2050

#define GEN5_AUD_CNTL_ST_A		0xE20B4

#define GEN5_ELD_BUFFER_SIZE		(0x1f << 10)

#define GEN5_ELD_ADDRESS		(0x1f << 5)

#define GEN5_ELD_ACK			(1 << 4)

#define GEN5_AUD_CNTL_ST2		0xE20C0

#define GEN5_ELD_VALIDB			(1 << 0)

#define GEN5_CP_READYB			(1 << 1)



#define GEN7_HDMIW_HDMIEDID_A		0xE5050

#define GEN7_AUD_CNTRL_ST_A		0xE50B4

#define GEN7_AUD_CNTRL_ST2		0xE50C0

#define IBX_HDMIW_HDMIEDID_A		0xE2050

#define IBX_AUD_CNTL_ST_A		0xE20B4

#define IBX_ELD_BUFFER_SIZE		(0x1f << 10)

#define IBX_ELD_ADDRESS			(0x1f << 5)

#define IBX_ELD_ACK			(1 << 4)

#define IBX_AUD_CNTL_ST2		0xE20C0

#define IBX_ELD_VALIDB			(1 << 0)

#define IBX_CP_READYB			(1 << 1)



#define CPT_HDMIW_HDMIEDID_A		0xE5050

#define CPT_AUD_CNTL_ST_A		0xE50B4

#define CPT_AUD_CNTRL_ST2		0xE50C0



#endif /* _I915_REG_H_ */

drivers/gpu/drm/i915/intel_display.c

+11 −11
Original line number Diff line number Diff line
@@ -5877,13 +5877,13 @@ static void ironlake_write_eld(struct drm_connector *connector, 
	int aud_cntrl_st2;



	if (HAS_PCH_IBX(connector->dev)) {

		hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;

		aud_cntl_st = GEN5_AUD_CNTL_ST_A;

		aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;

		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;

		aud_cntl_st = IBX_AUD_CNTL_ST_A;

		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;

	} else {

		hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;

		aud_cntl_st = GEN7_AUD_CNTRL_ST_A;

		aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;

		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;

		aud_cntl_st = CPT_AUD_CNTL_ST_A;

		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;

	}



	i = to_intel_crtc(crtc)->pipe;
@@ -5897,12 +5897,12 @@ static void ironlake_write_eld(struct drm_connector *connector, 
	if (!i) {

		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");

		/* operate blindly on all ports */

		eldv = GEN5_ELD_VALIDB;

		eldv |= GEN5_ELD_VALIDB << 4;

		eldv |= GEN5_ELD_VALIDB << 8;

		eldv = IBX_ELD_VALIDB;

		eldv |= IBX_ELD_VALIDB << 4;

		eldv |= IBX_ELD_VALIDB << 8;

	} else {

		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);

		eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);

		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);

	}



	i = I915_READ(aud_cntrl_st2);
@@ -5918,7 +5918,7 @@ static void ironlake_write_eld(struct drm_connector *connector, 
	}



	i = I915_READ(aud_cntl_st);

	i &= ~GEN5_ELD_ADDRESS;

	i &= ~IBX_ELD_ADDRESS;

	I915_WRITE(aud_cntl_st, i);



	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */