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Commit 11af9699 authored by Vandana Jain's avatar Vandana Jain
Browse files

msm: camera: Update SDM439 csiphy driver 



Add DDL tuning settings.

Change-Id: Ib03ded16a37bdc6102aaee92096ec5749a2684c9
Signed-off-by: default avatarVandana Jain <vandja@codeaurora.org>
parent 1b28a7b8

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h

+5 −1
Original line number Original line Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -73,6 +73,10 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { 
	{0x12c, 0x0},    /* mipi_csiphy_rx_lane_0_7_00 */

	{0x12c, 0x0},    /* mipi_csiphy_rx_lane_0_7_00 */

	{0x220, 0x0},    /* mipi_csiphy_rx_lane_1_7_00 */

	{0x220, 0x0},    /* mipi_csiphy_rx_lane_1_7_00 */

	{0xCC, 0x0},     /* mipi_csiphy_rx_clk_lane_7_00 */

	{0xCC, 0x0},     /* mipi_csiphy_rx_clk_lane_7_00 */

	{0x1F8, 0x20},   /* mipi_csiphy_rx_lane0_ddl_2_00 */

	{0x1FC, 0x10},   /* mipi_csiphy_rx_lane0_ddl_3_00 */

	{0x22C, 0x80},   /* mipi_csiphy_rx_lane_1_10_00 */

	{0x230, 0x10},   /* mipi_csiphy_rx_lane_1_11_00 */

};

};





static struct snps_freq_value snps_v100_freq_values[] = {

static struct snps_freq_value snps_v100_freq_values[] = {

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+26 −0
Original line number Original line Diff line number Diff line
@@ -292,6 +292,32 @@ static int msm_csiphy_snps_2_lane_config( 
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_cb_2_00.addr + offset);

		.mipi_csiphy_rx_cb_2_00.addr + offset);





	if (local_data_rate <= 1500) {

		msm_camera_io_w(

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_2_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_2_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_3_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_3_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_10_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_10_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_11_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_11_00.addr + offset);

	}

	return 0;

	return 0;

}

}

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h

+5 −1
Original line number Original line Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2011-2018, 2020, The Linux Foundation. All rights reserved.

/* Copyright (c) 2011-2018, 2020-2021, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -100,6 +100,10 @@ struct csiphy_reg_snps_parms_t { 
	struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_2_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_3_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_10_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_11_00;

};

};





struct csiphy_reg_3ph_parms_t {

struct csiphy_reg_3ph_parms_t {