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Commit 119608a7 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/kms/nv50-: handle degamma LUT from window channels 



Required to eventually support DRM colour management APIs, and to
support Volta.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e349a05d

drivers/gpu/drm/nouveau/dispnv50/Kbuild

+1 −0
Original line number Diff line number Diff line 
nouveau-y += dispnv50/disp.o

nouveau-y += dispnv50/lut.o



nouveau-y += dispnv50/core.o

nouveau-y += dispnv50/core507d.o

drivers/gpu/drm/nouveau/dispnv50/atom.h

+19 −6
Original line number Diff line number Diff line
@@ -16,6 +16,11 @@ struct nv50_atom { 
struct nv50_head_atom {

	struct drm_crtc_state state;



	struct {

		u32 mask;

		u32 olut;

	} wndw;



	struct {

		u16 iW;

		u16 iH;
@@ -47,8 +52,9 @@ struct nv50_head_atom { 
		bool visible;

		u32 handle;

		u64 offset:40;

		u8 buffer:1;

		u8 mode:4;

	} ilut;

	} olut;



	struct {

		bool visible;
@@ -107,7 +113,7 @@ struct nv50_head_atom { 


	union nv50_head_atom_mask {

		struct {

			bool ilut:1;

			bool olut:1;

			bool core:1;

			bool curs:1;

			bool view:1;
@@ -136,6 +142,7 @@ nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) 
struct nv50_wndw_atom {

	struct drm_plane_state state;



	struct drm_property_blob *ilut;

	bool visible;



	struct {
@@ -152,8 +159,14 @@ struct nv50_wndw_atom { 
	} sema;



	struct {

		u32 handle;

		struct {

			u64 offset:40;

			u8  buffer:1;

			u8  enable:2;

	} lut;

			u8  mode:4;

		} i;

	} xlut;



	struct {

		u8  mode:2;
@@ -180,8 +193,8 @@ struct nv50_wndw_atom { 
		struct {

			bool ntfy:1;

			bool sema:1;

			bool xlut:1;

			bool image:1;

			bool lut:1;

			bool point:1;

		};

		u8 mask;

drivers/gpu/drm/nouveau/dispnv50/base.h

+2 −1
Original line number Diff line number Diff line
@@ -17,8 +17,9 @@ void base507c_ntfy_reset(struct nouveau_bo *, u32); 
void base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_ntfy_clr(struct nv50_wndw *);

int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *);

void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_xlut_clr(struct nv50_wndw *);

void base507c_image_clr(struct nv50_wndw *);

void base507c_lut(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_update(struct nv50_wndw *, u32 *);



int base827c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **);

drivers/gpu/drm/nouveau/dispnv50/base507c.c

+30 −14
Original line number Diff line number Diff line
@@ -39,17 +39,6 @@ base507c_update(struct nv50_wndw *wndw, u32 *interlock) 
	}

}



void

base507c_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)

{

	u32 *push;

	if ((push = evo_wait(&wndw->wndw, 2))) {

		evo_mthd(push, 0x00e0, 1);

		evo_data(push, asyw->lut.enable << 30);

		evo_kick(push, &wndw->wndw);

	}

}



void

base507c_image_clr(struct nv50_wndw *wndw)

{
@@ -86,6 +75,28 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 
	}

}



void

base507c_xlut_clr(struct nv50_wndw *wndw)

{

	u32 *push;

	if ((push = evo_wait(&wndw->wndw, 2))) {

		evo_mthd(push, 0x00e0, 1);

		evo_data(push, 0x00000000);

		evo_kick(push, &wndw->wndw);

	}

}



void

base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)

{

	u32 *push;

	if ((push = evo_wait(&wndw->wndw, 2))) {

		evo_mthd(push, 0x00e0, 1);

		evo_data(push, 0x40000000);

		evo_kick(push, &wndw->wndw);

	}

}



int

base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset,

			 struct nvif_device *device)
@@ -177,14 +188,17 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, 
	if (ret)

		return ret;



	if (!wndw->func->ilut) {

		if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1))

			asyh->state.color_mgmt_changed = true;

	}



	asyh->base.depth = fb->format->depth;

	asyh->base.cpp = fb->format->cpp[0];

	asyh->base.x = asyw->state.src.x1 >> 16;

	asyh->base.y = asyw->state.src.y1 >> 16;

	asyh->base.w = asyw->state.fb->width;

	asyh->base.h = asyw->state.fb->height;



	asyw->lut.enable = 1;

	return 0;

}
@@ -213,9 +227,11 @@ base507c = { 
	.ntfy_set = base507c_ntfy_set,

	.ntfy_clr = base507c_ntfy_clr,

	.ntfy_wait_begun = base507c_ntfy_wait_begun,

	.olut_core = 1,

	.xlut_set = base507c_xlut_set,

	.xlut_clr = base507c_xlut_clr,

	.image_set = base507c_image_set,

	.image_clr = base507c_image_clr,

	.lut = base507c_lut,

	.update = base507c_update,

};

drivers/gpu/drm/nouveau/dispnv50/base827c.c

+3 −1
Original line number Diff line number Diff line
@@ -53,9 +53,11 @@ base827c = { 
	.ntfy_set = base507c_ntfy_set,

	.ntfy_clr = base507c_ntfy_clr,

	.ntfy_wait_begun = base507c_ntfy_wait_begun,

	.olut_core = 1,

	.xlut_set = base507c_xlut_set,

	.xlut_clr = base507c_xlut_clr,

	.image_set = base827c_image_set,

	.image_clr = base507c_image_clr,

	.lut = base507c_lut,

	.update = base507c_update,

};