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Commit 10607864 authored by Martin Schwidefsky's avatar Martin Schwidefsky
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s390/mm,tlb: correct tlb flush on page table upgrade



The IDTE instruction used to flush TLB entries for a specific address
space uses the address-space-control element (ASCE) to identify
affected TLB entries. The upgrade of a page table adds a new top
level page table which changes the ASCE. The TLB entries associated
with the old ASCE need to be flushed and the ASCE for the address space
needs to be replaced synchronously on all CPUs which currently use it.
The concept of a lazy ASCE update with an exception handler is broken.

Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent be39f196
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+0 −2
Original line number Diff line number Diff line
@@ -144,9 +144,7 @@ struct stack_frame {
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	__tlb_flush_mm(current->mm);					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
	update_mm(current->mm, current);				\
	execve_tail();							\
} while (0)

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ asmlinkage void do_syscall_trace_exit(struct pt_regs *regs);

void do_protection_exception(struct pt_regs *regs);
void do_dat_exception(struct pt_regs *regs);
void do_asce_exception(struct pt_regs *regs);

void addressing_exception(struct pt_regs *regs);
void data_exception(struct pt_regs *regs);
+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ PGM_CHECK_DEFAULT /* 34 */
PGM_CHECK_DEFAULT			/* 35 */
PGM_CHECK_DEFAULT			/* 36 */
PGM_CHECK_DEFAULT			/* 37 */
PGM_CHECK_64BIT(do_asce_exception)	/* 38 */
PGM_CHECK_DEFAULT			/* 38 */
PGM_CHECK_64BIT(do_dat_exception)	/* 39 */
PGM_CHECK_64BIT(do_dat_exception)	/* 3a */
PGM_CHECK_64BIT(do_dat_exception)	/* 3b */
+0 −37
Original line number Diff line number Diff line
@@ -423,43 +423,6 @@ void __kprobes do_dat_exception(struct pt_regs *regs)
		do_fault_error(regs, fault);
}

#ifdef CONFIG_64BIT
void __kprobes do_asce_exception(struct pt_regs *regs)
{
	struct mm_struct *mm = current->mm;
	struct vm_area_struct *vma;
	unsigned long trans_exc_code;

	/*
	 * The instruction that caused the program check has
	 * been nullified. Don't signal single step via SIGTRAP.
	 */
	clear_tsk_thread_flag(current, TIF_PER_TRAP);

	trans_exc_code = regs->int_parm_long;
	if (unlikely(!user_space_fault(trans_exc_code) || in_atomic() || !mm))
		goto no_context;

	down_read(&mm->mmap_sem);
	vma = find_vma(mm, trans_exc_code & __FAIL_ADDR_MASK);
	up_read(&mm->mmap_sem);

	if (vma) {
		update_mm(mm, current);
		return;
	}

	/* User mode accesses just cause a SIGSEGV */
	if (user_mode(regs)) {
		do_sigsegv(regs, SEGV_MAPERR);
		return;
	}

no_context:
	do_no_context(regs);
}
#endif

int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
{
	struct pt_regs regs;
+2 −10
Original line number Diff line number Diff line
@@ -101,18 +101,12 @@ void arch_pick_mmap_layout(struct mm_struct *mm)

int s390_mmap_check(unsigned long addr, unsigned long len, unsigned long flags)
{
	int rc;

	if (is_compat_task() || (TASK_SIZE >= (1UL << 53)))
		return 0;
	if (!(flags & MAP_FIXED))
		addr = 0;
	if ((addr + len) >= TASK_SIZE) {
		rc = crst_table_upgrade(current->mm, 1UL << 53);
		if (rc)
			return rc;
		update_mm(current->mm, current);
	}
	if ((addr + len) >= TASK_SIZE)
		return crst_table_upgrade(current->mm, 1UL << 53);
	return 0;
}

@@ -132,7 +126,6 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr,
		rc = crst_table_upgrade(mm, 1UL << 53);
		if (rc)
			return (unsigned long) rc;
		update_mm(mm, current);
		area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);
	}
	return area;
@@ -155,7 +148,6 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr,
		rc = crst_table_upgrade(mm, 1UL << 53);
		if (rc)
			return (unsigned long) rc;
		update_mm(mm, current);
		area = arch_get_unmapped_area_topdown(filp, addr, len,
						      pgoff, flags);
	}
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