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Commit 0ff3758b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-nc-4.11' of... 

Merge tag 'imx-fixes-nc-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX non-critical device tree fixes for 4.11:
 - A couple of fixes on anatop regulator voltage and constraints
   according to hardware datasheet.
 - Correct FEC interrupt routing for i.MX6QP which has got the hardware
   bug found on i.MX6Q fixed.
 - Remove unit address from i.MX6 LDB device node to fix DTC warning.
 - A fix on imx53-qsb board FEC pinmux config to remove the dependency
   on firmware for setting up pins.
 - A series from Sascha to fix LPSR pins for i.MX7 boards.

* tag 'imx-fixes-nc-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  ARM: dts: imx53-qsb-common: fix FEC pinmux config
  ARM: imx6: remove unit address from LDB node
  ARM: imx6qp: adapt DT to changed FEC interrupts
  ARM: imx6: fix regulator constraints on anatop 1p1 and 2p5
  ARM: imx6: fix min/max voltage of anatop 2p5 regulator
  ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names
  ARM: dts: imx7d-cl-som: Fix OTG power pinctrl
  ARM: dts: imx7d-sdb: Fix watchdog and pwm pinmux
  ARM: dts: imx7s-warp: Fix watchdog pinmux

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3c63c24d 8b649e42

arch/arm/boot/dts/imx53-qsb-common.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -215,16 +215,16 @@ 


		pinctrl_fec: fecgrp {

			fsl,pins = <

				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000

				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000

				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000

				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000

				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000

				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000

				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000

				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000

				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000

				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000

				MX53_PAD_FEC_MDC__FEC_MDC		0x4

				MX53_PAD_FEC_MDIO__FEC_MDIO		0x1fc

				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x180

				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x180

				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x180

				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x180

				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x180

				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x4

				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x4

				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x4

			>;

		};

arch/arm/boot/dts/imx6qdl.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -626,8 +626,8 @@ 
				regulator-1p1 {

					compatible = "fsl,anatop-regulator";

					regulator-name = "vdd1p1";

					regulator-min-microvolt = <800000>;

					regulator-max-microvolt = <1375000>;

					regulator-min-microvolt = <1000000>;

					regulator-max-microvolt = <1200000>;

					regulator-always-on;

					anatop-reg-offset = <0x110>;

					anatop-vol-bit-shift = <8>;
@@ -654,15 +654,15 @@ 
				regulator-2p5 {

					compatible = "fsl,anatop-regulator";

					regulator-name = "vdd2p5";

					regulator-min-microvolt = <2000000>;

					regulator-min-microvolt = <2250000>;

					regulator-max-microvolt = <2750000>;

					regulator-always-on;

					anatop-reg-offset = <0x130>;

					anatop-vol-bit-shift = <8>;

					anatop-vol-bit-width = <5>;

					anatop-min-bit-val = <0>;

					anatop-min-voltage = <2000000>;

					anatop-max-voltage = <2750000>;

					anatop-min-voltage = <2100000>;

					anatop-max-voltage = <2875000>;

				};



				reg_arm: regulator-vddcore {
@@ -808,7 +808,7 @@ 
				reg = <0x020e0000 0x4000>;

			};



			ldb: ldb@020e0008 {

			ldb: ldb {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";

arch/arm/boot/dts/imx6qp.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -95,6 +95,12 @@ 
	};

};



&fec {

	/delete-property/interrupts-extended;

	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,

		     <0 119 IRQ_TYPE_LEVEL_HIGH>;

};



&ldb {

	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,

		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,

arch/arm/boot/dts/imx7-colibri.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -596,29 +596,29 @@ 


	pinctrl_gpio_lpsr: gpio1-grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO01__GPIO1_IO1	0x59

			MX7D_PAD_GPIO1_IO02__GPIO1_IO2	0x59

			MX7D_PAD_GPIO1_IO03__GPIO1_IO3	0x59

			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x59

			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59

			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59

		>;

	};



	pinctrl_i2c1: i2c1-grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO05__I2C1_SDA	0x4000007f

			MX7D_PAD_GPIO1_IO04__I2C1_SCL	0x4000007f

			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f

			MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f

		>;

	};



	pinctrl_cd_usdhc1: usdhc1-cd-grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */

			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */

		>;

	};



	pinctrl_uart1_ctrl2: uart1-ctrl2-grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO07__GPIO1_IO7	0x14 /* DSR */

			MX7D_PAD_GPIO1_IO06__GPIO1_IO6	0x14 /* RI */

			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* DSR */

			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* RI */

		>;

	};

};

arch/arm/boot/dts/imx7d-cl-som-imx7.dts

+8 −6
Original line number Diff line number Diff line
@@ -261,12 +261,6 @@ 
		>;

	};



	pinctrl_usbotg1: usbotg1grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO05__GPIO1_IO5		0x14 /* OTG PWREN */

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
@@ -283,3 +277,11 @@ 
		>;

	};

};



&iomuxc_lpsr {

	pinctrl_usbotg1: usbotg1grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x14 /* OTG PWREN */

		>;

	};

};
 
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