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Commit 0fc899b0 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: Enable double buffer as per vertical interrupt enabled. 



Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09f2317b

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -299,6 +299,17 @@ static void tgn10_program_timing( 
static void tgn10_unblank_crtc(struct timing_generator *tg)

static void tgn10_unblank_crtc(struct timing_generator *tg)

{

{

	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);

	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);

	uint32_t vertical_interrupt_enable = 0;



	REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,

			OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);



	/* temporary work around for vertical interrupt, once vertical interrupt enabled,

	 * this check will be removed.

	 */

	if (vertical_interrupt_enable)

		REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,

				OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1);





	REG_UPDATE_2(OTG_BLANK_CONTROL,

	REG_UPDATE_2(OTG_BLANK_CONTROL,

			OTG_BLANK_DATA_EN, 0,

			OTG_BLANK_DATA_EN, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -65,6 +65,7 @@ 
	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\

	SRI(OTG_BLACK_COLOR, OTG, inst),\

	SRI(OTG_BLACK_COLOR, OTG, inst),\

	SRI(OTG_CLOCK_CONTROL, OTG, inst),\

	SRI(OTG_CLOCK_CONTROL, OTG, inst),\

	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\

	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\

	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\

	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\

	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
@@ -117,6 +118,7 @@ struct dcn_tg_registers { 
	uint32_t OTG_TEST_PATTERN_CONTROL;

	uint32_t OTG_TEST_PATTERN_CONTROL;

	uint32_t OTG_TEST_PATTERN_COLOR;

	uint32_t OTG_TEST_PATTERN_COLOR;

	uint32_t OTG_CLOCK_CONTROL;

	uint32_t OTG_CLOCK_CONTROL;

	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;

	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;

	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;

	uint32_t OPTC_INPUT_CLOCK_CONTROL;

	uint32_t OPTC_INPUT_CLOCK_CONTROL;

	uint32_t OPTC_DATA_SOURCE_SELECT;

	uint32_t OPTC_DATA_SOURCE_SELECT;
@@ -196,6 +198,7 @@ struct dcn_tg_registers { 
	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\

	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\

	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\

	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\

	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\

	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\

	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\

	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\

	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\

	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\

	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\

	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\

	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
@@ -302,6 +305,7 @@ struct dcn_tg_registers { 
	type OTG_CLOCK_EN;\

	type OTG_CLOCK_EN;\

	type OTG_CLOCK_ON;\

	type OTG_CLOCK_ON;\

	type OTG_CLOCK_GATE_DIS;\

	type OTG_CLOCK_GATE_DIS;\

	type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\

	type OTG_VERTICAL_INTERRUPT2_LINE_START;\

	type OTG_VERTICAL_INTERRUPT2_LINE_START;\

	type OPTC_INPUT_CLK_EN;\

	type OPTC_INPUT_CLK_EN;\

	type OPTC_INPUT_CLK_ON;\

	type OPTC_INPUT_CLK_ON;\