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Commit 0f94b0af authored by Ivan Safonov's avatar Ivan Safonov Committed by Greg Kroah-Hartman
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staging: rtl8188eu: remove PWR_BASEADDR_* macro definitions and "base" member... 


staging: rtl8188eu: remove PWR_BASEADDR_* macro definitions and "base" member of wl_pwr_cfg structure

These macros and "base" member of wl_pwr_cfg structure
are used only to produce debug output.

Signed-off-by: default avatarIvan Safonov <insafonov@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0e54dbd4

drivers/staging/rtl8188eu/hal/pwrseqcmd.c

+1 −2
Original line number Diff line number Diff line
@@ -39,11 +39,10 @@ u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, 


		RT_TRACE(_module_hal_init_c_, _drv_info_,

			 ("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)"

			  " base(%#x) cmd(%#x)"

			  " cmd(%#x)"

			  "msk(%#x) value(%#x)\n",

			 GET_PWR_CFG_OFFSET(pwrcfgcmd),

			 GET_PWR_CFG_CUT_MASK(pwrcfgcmd),

			 GET_PWR_CFG_BASE(pwrcfgcmd),

			 GET_PWR_CFG_CMD(pwrcfgcmd),

			 GET_PWR_CFG_MASK(pwrcfgcmd),

			 GET_PWR_CFG_VALUE(pwrcfgcmd)));

drivers/staging/rtl8188eu/include/pwrseq.h

+62 −103
Original line number Diff line number Diff line
@@ -60,213 +60,172 @@ 


#define RTL8188E_TRANS_CARDEMU_TO_ACT					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk, value

	 * { offset, cut_msk, cmd, msk, value

	 * },

	 * comment here

	 */								\

	{0x0006, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},		\

	{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \

	/* wait till 0x04[17] = 1    power ready*/	\

	{0x0002, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0},		\

	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \

	/* 0x02[1:0] = 0	reset BB*/				\

	{0x0026, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},		\

	{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \

	/*0x24[23] = 2b'01 schmit trigger */				\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \

	/* 0x04[15] = 0 disable HWPDN (control by DRV)*/		\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \

	/*0x04[12:11] = 2b'00 disable WL suspend*/			\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \

	/*0x04[8] = 1 polling until return 0*/				\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \

	/*wait till 0x04[8] = 0*/					\

	{0x0023, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\

	{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \

	/*LDO normal mode*/



#define RTL8188E_TRANS_ACT_TO_CARDEMU					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk, value

	 * { offset, cut_msk, cmd, msk, value

	 * },

	 * comments here

	 */								\

	{0x001F, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},			\

	{0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \

	/*0x1F[7:0] = 0 turn off RF*/					\

	{0x0023, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},		\

	{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \

	/*LDO Sleep mode*/						\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \

	/*0x04[9] = 1 turn off MAC by HW state machine*/		\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \

	/*wait till 0x04[9] = 0 polling until return 0 to disable*/



#define RTL8188E_TRANS_CARDEMU_TO_SUS					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \

	/* 0x04[12:11] = 2b'01enable WL suspend */			\

	{0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, 0xFF, BIT(7)},					\

	{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \

	/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\

	{0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, BIT(4), 0},					\

	{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \

	/*Clear SIC_EN register 0x40[12] = 1'b0 */			\

	{0xfe10, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, BIT(4), BIT(4)},					\

	{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \

	/*Set USB suspend enable local register  0xfe10[4]=1 */



#define RTL8188E_TRANS_SUS_TO_CARDEMU					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \

	/*0x04[12:11] = 2b'01enable WL suspend*/



#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS				\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0026, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},		\

	{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \

	/*0x24[23] = 2b'01 schmit trigger */				\

	{0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \

	/*0x04[12:11] = 2b'01 enable WL suspend*/			\

	{0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, 0xFF, 0},					\

	{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \

	/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\

	{0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC,		\

	PWR_CMD_WRITE, BIT(4), 0},					\

	{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \

	/*Clear SIC_EN register 0x40[12] = 1'b0 */			\

	{0xfe10, PWR_CUT_ALL_MSK,	\

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},		\

	{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \

	/*Set USB suspend enable local register  0xfe10[4]=1 */



#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU				\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \

	/*0x04[12:11] = 2b'01enable WL suspend*/



#define RTL8188E_TRANS_CARDEMU_TO_PDN					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0006, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\

	{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \

	/* 0x04[16] = 0*/						\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},		\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \

	/* 0x04[15] = 1*/



#define RTL8188E_TRANS_PDN_TO_CARDEMU					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0005, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},			\

	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \

	/* 0x04[15] = 0*/



/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */

#define RTL8188E_TRANS_ACT_TO_LPS					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0x0522, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\

	{0x05F8, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\

	{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \

	{0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \

	/*Should be zero if no packet is transmitting*/			\

	{0x05F9, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\

	{0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \

	/*Should be zero if no packet is transmitting*/			\

	{0x05FA, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\

	{0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \

	/*Should be zero if no packet is transmitting*/			\

	{0x05FB, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\

	{0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \

	/*Should be zero if no packet is transmitting*/			\

	{0x0002, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\

	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \

	/*CCK and OFDM are disabled,and clock are gated*/		\

	{0x0002, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0,				\

	PWRSEQ_DELAY_US},/*Delay 1us*/					\

	{0x0100, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\

	{0x0101, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\

	{0x0553, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},		\

	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0,	PWRSEQ_DELAY_US}, \

	/*Delay 1us*/ \

	{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \

	/*Reset MAC TRX*/ \

	{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \

	/*check if removed later*/\

	{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \

	/*Respond TxOK to scheduler*/





#define RTL8188E_TRANS_LPS_TO_ACT					\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0xFE58, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\

	{0x0002, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/	\

	{0x0008, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\

	{0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \

	/*USB RPWM*/	\

	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \

	/*Delay*/	\

	{0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \

	/* 0x08[4] = 0 switch TSF to 40M */				\

	{0x0109, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},			\

	{0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \

	/* Polling 0x109[7]=0  TSF in 40M */				\

	{0x0029, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0},		\

	{0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \

	/* 0x29[7:6] = 2b'00  enable BB clock */			\

	{0x0101, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\

	{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \

	/* 0x101[1] = 1 */						\

	{0x0100, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},			\

	{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \

	/* 0x100[7:0] = 0xFF enable WMAC TRX */				\

	{0x0002, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \

	PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \

	/* 0x02[1:0] = 2b'11 enable BB macro */				\

	{0x0522, PWR_CUT_ALL_MSK, \

	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/

	{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/



#define RTL8188E_TRANS_END						\

	/* format

	 * { offset, cut_msk, interface_msk, base|cmd, msk,

	 * { offset, cut_msk, cmd, msk,

	 * value },

	 * comments here

	 */								\

	{0xFFFF, PWR_CUT_ALL_MSK, 0,	\

	PWR_CMD_END, 0, 0},

	{0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},





extern struct wl_pwr_cfg rtl8188E_power_on_flow

drivers/staging/rtl8188eu/include/pwrseqcmd.h

+0 −9
Original line number Diff line number Diff line
@@ -29,13 +29,6 @@ 
#define PWR_CMD_DELAY		0x03

#define PWR_CMD_END		0x04



/* The value of base: 4 bits */

/*  define the base address of each block */

#define PWR_BASEADDR_MAC	0x00

#define PWR_BASEADDR_USB	0x01

#define PWR_BASEADDR_PCIE	0x02

#define PWR_BASEADDR_SDIO	0x03



/* The value of cut_msk: 8 bits */

#define PWR_CUT_TESTCHIP_MSK	BIT(0)

#define PWR_CUT_A_MSK		BIT(1)
@@ -56,7 +49,6 @@ enum pwrseq_cmd_delat_unit { 
struct wl_pwr_cfg {

	u16 offset;

	u8 cut_msk;

	u8 base:4;

	u8 cmd:4;

	u8 msk;

	u8 value;
@@ -64,7 +56,6 @@ struct wl_pwr_cfg { 


#define GET_PWR_CFG_OFFSET(__PWR_CMD)		__PWR_CMD.offset

#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		__PWR_CMD.cut_msk

#define GET_PWR_CFG_BASE(__PWR_CMD)		__PWR_CMD.base

#define GET_PWR_CFG_CMD(__PWR_CMD)		__PWR_CMD.cmd

#define GET_PWR_CFG_MASK(__PWR_CMD)		__PWR_CMD.msk

#define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value