Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0f6ca3ba authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Add function to get optc active size 



Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 73770ca5

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+32 −0
Original line number Diff line number Diff line
@@ -1257,6 +1257,37 @@ void optc1_read_otg_state(struct optc *optc1, 
			OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);

}



bool optc1_get_otg_active_size(struct timing_generator *optc,

		uint32_t *otg_active_width,

		uint32_t *otg_active_height)

{

	uint32_t otg_enabled;

	uint32_t v_blank_start;

	uint32_t v_blank_end;

	uint32_t h_blank_start;

	uint32_t h_blank_end;

	struct optc *optc1 = DCN10TG_FROM_TG(optc);





	REG_GET(OTG_CONTROL,

			OTG_MASTER_EN, &otg_enabled);



	if (otg_enabled == 0)

		return false;



	REG_GET_2(OTG_V_BLANK_START_END,

			OTG_V_BLANK_START, &v_blank_start,

			OTG_V_BLANK_END, &v_blank_end);



	REG_GET_2(OTG_H_BLANK_START_END,

			OTG_H_BLANK_START, &h_blank_start,

			OTG_H_BLANK_END, &h_blank_end);



	*otg_active_width = v_blank_start - v_blank_end;

	*otg_active_height = h_blank_start - h_blank_end;

	return true;

}



void optc1_clear_optc_underflow(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -1305,6 +1336,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { 
		.get_position = optc1_get_position,

		.get_frame_count = optc1_get_vblank_counter,

		.get_scanoutpos = optc1_get_crtc_scanoutpos,

		.get_otg_active_size = optc1_get_otg_active_size,

		.set_early_control = optc1_set_early_control,

		/* used by enable_timing_synchronization. Not need for FPGA */

		.wait_for_state = optc1_wait_for_state,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+4 −0
Original line number Diff line number Diff line
@@ -507,4 +507,8 @@ bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 


void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);



bool optc1_get_otg_active_size(struct timing_generator *optc,

		uint32_t *otg_active_width,

		uint32_t *otg_active_height);



#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

+3 −0
Original line number Diff line number Diff line
@@ -156,6 +156,9 @@ struct timing_generator_funcs { 
		uint32_t *v_blank_end,

		uint32_t *h_position,

		uint32_t *v_position);

	bool (*get_otg_active_size)(struct timing_generator *optc,

			uint32_t *otg_active_width,

			uint32_t *otg_active_height);

	void (*set_early_control)(struct timing_generator *tg,

							   uint32_t early_cntl);

	void (*wait_for_state)(struct timing_generator *tg,