Commit 0f2fa40e authored Jan 23, 2013 by Maxime Coquelin Committed by Linus Walleij Mar 18, 2013

ARM: mach-ux500: enable 128KB way L2 cache on DB8540



DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.

Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
cpus in the x540 family.

Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

parent cca438b5

arch/arm/mach-ux500/cache-l2x0.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void)
		/* Unlock before init */
		ux500_l2x0_unlock();

		/* DB9540's L2 has 128KB way size */
		if (cpu_is_u9540())
		/* DBx540's L2 has 128KB way size */
		if (cpu_is_ux540_family())
		/* 128KB way size */
		aux_val \|= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
		else