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Commit 0f166396 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (62 commits)
  [MIPS] PNX8550: Cleanup proc code.
  [MIPS] WRPPMC: Fix build.
  [MIPS] Yosemite: Fix modpost warnings.
  [MIPS] Change names of local variables to silence sparse
  [MIPS] SB1: Fix modpost warning.
  [MIPS] PNX: Fix modpost warnings.
  [MIPS] Alchemy: Fix modpost warnings.
  [MIPS] Non-FPAFF: Fix warning.
  [MIPS] DEC: Fix modpost warning.
  [MIPS] MIPSsim: Enable MIPSsim virtual network driver.
  [MIPS] Delete Ocelot 3 support.
  [MIPS] remove LASAT Networks platforms support
  [MIPS] Early check for SMTC kernel on non-MT processor
  [MIPS] Add debugfs files to show fpuemu statistics
  [MIPS] Add some debugfs files to debug unaligned accesses
  [MIPS] rbtx4938: Fix secondary PCIC and glue internal NICs
  [MIPS] tc35815: Load MAC address via platform_device
  [MIPS] Move FPU affinity code into separate file.
  [MIPS] Make ioremap() work on TX39/49 special unmapped segment
  [MIPS] rbtx4938: Update and minimize defconfig
  ...
parents 5f60cfd9 105b1bca

arch/mips/Kconfig

+93 −105
Original line number Diff line number Diff line
@@ -15,6 +15,29 @@ choice 
	prompt "System type"

	default SGI_IP22



config LEMOTE_FULONG

	bool "Lemote Fulong mini-PC"

	select ARCH_SPARSEMEM_ENABLE

	select SYS_HAS_CPU_LOONGSON2

	select DMA_NONCOHERENT

	select BOOT_ELF32

	select BOARD_SCACHE

	select HAVE_STD_PC_SERIAL_PORT

	select HW_HAS_PCI

	select I8259

	select ISA

	select IRQ_CPU

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_HAS_EARLY_PRINTK

	select GENERIC_HARDIRQS_NO__DO_IRQ

	select CPU_HAS_WB

	help

	  Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and

	  an FPGA northbridge



config MACH_ALCHEMY

	bool "Alchemy processor based machines"
@@ -63,7 +86,7 @@ config MACH_DECSTATION 
	bool "DECstations"

	select BOOT_ELF32

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select NO_IOPORT

	select IRQ_CPU

	select SYS_HAS_CPU_R3000

	select SYS_HAS_CPU_R4X00
@@ -88,24 +111,6 @@ config MACH_DECSTATION 


	  otherwise choose R3000.



config MIPS_EV64120

	bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)"

	depends on EXPERIMENTAL

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select PCI_GT64XXX_PCI0

	select SYS_HAS_CPU_R5000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_KGDB

	help

	  This is an evaluation board based on the Galileo GT-64120

	  single-chip system controller that contains a MIPS R5000 compatible

	  core running at 75/100MHz.  Their website is located at

	  <http://www.marvell.com/>.  Say Y here if you wish to build a

	  kernel for this platform.



config MACH_JAZZ

	bool "Jazz family of machines"

	select ARC
@@ -126,20 +131,6 @@ config MACH_JAZZ 
	 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and

	 Olivetti M700-10 workstations.



config LASAT

	bool "LASAT Networks platforms"

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select HW_HAS_PCI

	select PCI_GT64XXX_PCI0

	select MIPS_NILE4

	select R5000_CPU_SCACHE

	select SYS_HAS_CPU_R5000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL if BROKEN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select GENERIC_HARDIRQS_NO__DO_IRQ



config MIPS_ATLAS

	bool "MIPS Atlas board"

	select BOOT_ELF32
@@ -173,7 +164,6 @@ config MIPS_MALTA 
	bool "MIPS Malta board"

	select ARCH_MAY_HAVE_PC_FDC

	select BOOT_ELF32

	select HAVE_STD_PC_SERIAL_PORT

	select DMA_NONCOHERENT

	select GENERIC_ISA_DMA

	select IRQ_CPU
@@ -246,11 +236,13 @@ config MIPS_SIM 
	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select IRQ_CPU

	select BOOT_RAW

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MULTITHREADING

	select SYS_SUPPORTS_LITTLE_ENDIAN

	help

	  This option enables support for MIPS Technologies MIPSsim software
@@ -274,43 +266,6 @@ config MOMENCO_OCELOT 
	  The Ocelot is a MIPS-based Single Board Computer (SBC) made by

	  Momentum Computer <http://www.momenco.com/>.



config MOMENCO_OCELOT_3

	bool "Momentum Ocelot-3 board"

	select BOOT_ELF32

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU

	select IRQ_CPU_RM7K

	select IRQ_MV64340

	select PCI_MARVELL

	select RM7000_CPU_SCACHE

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_RM9000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	help

	  The Ocelot-3 is based off Discovery III System Controller and

	  PMC-Sierra Rm79000 core.



config MOMENCO_OCELOT_C

	bool "Momentum Ocelot-C board"

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU

	select IRQ_MV64340

	select PCI_MARVELL

	select RM7000_CPU_SCACHE

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_RM7000

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select GENERIC_HARDIRQS_NO__DO_IRQ

	help

	  The Ocelot is a MIPS-based Single Board Computer (SBC) made by

	  Momentum Computer <http://www.momenco.com/>.



config PNX8550_JBS

	bool "Philips PNX8550 based JBS board"

	select PNX8550
@@ -346,6 +301,27 @@ config MACH_VR41XX 
	select SYS_HAS_CPU_VR41XX

	select GENERIC_HARDIRQS_NO__DO_IRQ



config PMC_MSP

	bool "PMC-Sierra MSP chipsets"

	depends on EXPERIMENTAL

	select DMA_NONCOHERENT

	select SWAP_IO_SPACE

	select NO_EXCEPT_FILL

	select BOOT_RAW

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_KGDB

	select IRQ_CPU

	select SERIAL_8250

	select SERIAL_8250_CONSOLE

	help

	  This adds support for the PMC-Sierra family of Multi-Service

	  Processor System-On-A-Chips.  These parts include a number

	  of integrated peripherals, interfaces and DSPs in addition to

	  a variety of MIPS cores.



config PMC_YOSEMITE

	bool "PMC-Sierra Yosemite eval board"

	select DMA_COHERENT
@@ -450,8 +426,7 @@ config SGI_IP27 
	  here.



config SGI_IP32

	bool "SGI IP32 (O2) (EXPERIMENTAL)"

	depends on EXPERIMENTAL

	bool "SGI IP32 (O2)"

	select ARC

	select ARC32

	select BOOT_ELF32
@@ -652,6 +627,7 @@ config TOSHIBA_RBTX4938 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_KGDB

	select GENERIC_HARDIRQS_NO__DO_IRQ

	select GENERIC_GPIO

	help

	  This Toshiba board is based on the TX4938 processor. Say Y here to

	  support this machine type
@@ -660,9 +636,7 @@ endchoice 


source "arch/mips/au1000/Kconfig"

source "arch/mips/ddb5xxx/Kconfig"

source "arch/mips/gt64120/ev64120/Kconfig"

source "arch/mips/jazz/Kconfig"

source "arch/mips/lasat/Kconfig"

source "arch/mips/pmc-sierra/Kconfig"

source "arch/mips/sgi-ip27/Kconfig"

source "arch/mips/sibyte/Kconfig"
@@ -721,6 +695,9 @@ config ARC 
config ARCH_MAY_HAVE_PC_FDC

	bool



config BOOT_RAW

	bool



config DMA_COHERENT

	bool
@@ -768,16 +745,19 @@ config MIPS_BONITO64 
config MIPS_MSC

	bool



config MIPS_NILE4

	bool



config MIPS_DISABLE_OBSOLETE_IDE

	bool



config NO_IOPORT

	def_bool n



config GENERIC_ISA_DMA_SUPPORT_BROKEN

	bool

	select ZONE_DMA



config GENERIC_GPIO

	bool



#

# Endianess selection.  Sufficiently obscure so many users don't know what to

# answer,so we try hard to limit the available choices.  Also the use of a
@@ -821,7 +801,10 @@ config IRQ_CPU_RM7K 
config IRQ_CPU_RM9K

	bool



config IRQ_MV64340

config IRQ_MSP_SLP

	bool



config IRQ_MSP_CIC

	bool



config DDB5XXX_COMMON
@@ -834,6 +817,9 @@ config MIPS_BOARDS_GEN 
config PCI_GT64XXX_PCI0

	bool



config NO_EXCEPT_FILL

	bool



config MIPS_TX3927

	bool

	select HAS_TXX9_SERIAL
@@ -841,14 +827,6 @@ config MIPS_TX3927 
config MIPS_RM9122

	bool

	select SERIAL_RM9000

	select GPI_RM9000

	select WDT_RM9000



config PCI_MARVELL

	bool



config SERIAL_RM9000

	bool



config PNX8550

	bool
@@ -863,6 +841,7 @@ config SOC_PNX8550 
	select SYS_SUPPORTS_32BIT_KERNEL

	select GENERIC_HARDIRQS_NO__DO_IRQ

	select SYS_SUPPORTS_KGDB

	select GENERIC_GPIO



config SWAP_IO_SPACE

	bool
@@ -875,31 +854,17 @@ config EMMA2RH 
config SERIAL_RM9000

	bool



config GPI_RM9000

	bool



config WDT_RM9000

	bool



#

# Unfortunately not all GT64120 systems run the chip at the same clock.

# As the user for the clock rate and try to minimize the available options.

#

choice

	prompt "Galileo Chip Clock"

	#default SYSCLK_83 if MIPS_EV64120

	depends on MIPS_EV64120 || MOMENCO_OCELOT

	default SYSCLK_83 if MIPS_EV64120

	depends on MOMENCO_OCELOT

	default SYSCLK_100 if MOMENCO_OCELOT



config SYSCLK_75

	bool "75" if MIPS_EV64120



config SYSCLK_83

	bool "83.3" if MIPS_EV64120



config SYSCLK_100

	bool "100" if MIPS_EV64120 || MOMENCO_OCELOT

	bool "100" if MOMENCO_OCELOT



endchoice
@@ -911,8 +876,9 @@ config BOOT_ELF32 


config MIPS_L1_CACHE_SHIFT

	int

	default "4" if MACH_DECSTATION || SNI_RM

	default "7" if SGI_IP27

	default "4" if MACH_DECSTATION

	default "7" if SGI_IP27 || SNI_RM

	default "4" if PMC_MSP4200_EVAL

	default "5"



config HAVE_STD_PC_SERIAL_PORT
@@ -944,6 +910,16 @@ choice 
	prompt "CPU type"

	default CPU_R4X00



config CPU_LOONGSON2

	bool "Loongson 2"

	depends on SYS_HAS_CPU_LOONGSON2

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	help

	  The Loongson 2E processor implements the MIPS III instruction set

	  with many extensions.



config CPU_MIPS32_R1

	bool "MIPS32 Release 1"

	depends on SYS_HAS_CPU_MIPS32_R1
@@ -1154,6 +1130,9 @@ config CPU_SB1 


endchoice



config SYS_HAS_CPU_LOONGSON2

	bool



config SYS_HAS_CPU_MIPS32_R1

	bool
@@ -1488,6 +1467,15 @@ config CPU_HAS_SMARTMIPS 
config CPU_HAS_WB

	bool



config 64BIT_CONTEXT

	bool "Save 64bit integer registers"

	depends on 32BIT && CPU_LOONGSON2

	help

	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer

	  registers can still be accessed as 64bit, mainly for multimedia

	  instructions. We must have all 64bit save/restored to make sure

	  those instructions to get correct result.



#

# Vectored interrupt mode is an R2 feature

#

arch/mips/Makefile

+28 −56
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap 
cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap

cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap

cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap

cflags-$(CONFIG_CPU_LOONGSON2)	+= -march=r4600 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

			-Wa,-mips32 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -282,14 +283,6 @@ libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/ 
load-$(CONFIG_MACH_DECSTATION)	+= 0xffffffff80040000

CLEAN_FILES			+= drivers/tc/lk201-map.c



#

# Galileo EV64120 Board

#

core-$(CONFIG_MIPS_EV64120)	+= arch/mips/gt64120/ev64120/

core-$(CONFIG_MIPS_EV64120)	+= arch/mips/gt64120/common/

cflags-$(CONFIG_MIPS_EV64120)	+= -Iinclude/asm-mips/mach-ev64120

load-$(CONFIG_MIPS_EV64120)	+= 0xffffffff80100000



#

# Wind River PPMC Board (4KC + GT64120)

#
@@ -297,6 +290,13 @@ core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/ 
cflags-$(CONFIG_WR_PPMC)		+= -Iinclude/asm-mips/mach-wrppmc

load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000



#

# lemote fulong mini-PC board

#

core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/

load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000

cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote



#

# For all MIPS, Inc. eval boards

#
@@ -327,7 +327,7 @@ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 
#

# MIPS SIM

#

core-$(CONFIG_MIPS_SIM)		+= arch/mips/mips-boards/sim/

core-$(CONFIG_MIPS_SIM)		+= arch/mips/mipssim/

cflags-$(CONFIG_MIPS_SIM)	+= -Iinclude/asm-mips/mach-sim

load-$(CONFIG_MIPS_SIM)		+= 0x80100000
@@ -343,12 +343,12 @@ cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot 
load-$(CONFIG_MOMENCO_OCELOT)	+= 0xffffffff80100000



#

# Momentum Ocelot-C and -CS boards

# PMC-Sierra MSP SOCs

#

# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the

# mips_io_port_base.

core-$(CONFIG_MOMENCO_OCELOT_C)	+= arch/mips/momentum/ocelot_c/

load-$(CONFIG_MOMENCO_OCELOT_C)	+= 0xffffffff80100000

core-$(CONFIG_PMC_MSP)		+= arch/mips/pmc-sierra/msp71xx/

cflags-$(CONFIG_PMC_MSP)	+= -Iinclude/asm-mips/pmc-sierra/msp71xx \

					-mno-branch-likely

load-$(CONFIG_PMC_MSP)		+= 0xffffffff80100000



#

# PMC-Sierra Yosemite
@@ -364,13 +364,6 @@ core-$(CONFIG_QEMU) += arch/mips/qemu/ 
cflags-$(CONFIG_QEMU)		+= -Iinclude/asm-mips/mach-qemu

load-$(CONFIG_QEMU)		+= 0xffffffff80010000



#

# Momentum Ocelot-3

#

core-$(CONFIG_MOMENCO_OCELOT_3) 	+= arch/mips/momentum/ocelot_3/

cflags-$(CONFIG_MOMENCO_OCELOT_3)	+= -Iinclude/asm-mips/mach-ocelot3

load-$(CONFIG_MOMENCO_OCELOT_3) 	+= 0xffffffff80100000



#

# Basler eXcite

#
@@ -389,10 +382,6 @@ core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ 
core-$(CONFIG_DDB5477)		+= arch/mips/ddb5xxx/ddb5477/

load-$(CONFIG_DDB5477)		+= 0xffffffff80100000



core-$(CONFIG_LASAT)		+= arch/mips/lasat/

cflags-$(CONFIG_LASAT)		+= -Iinclude/asm-mips/mach-lasat

load-$(CONFIG_LASAT)		+= 0xffffffff80000000



#

# Common VR41xx

#
@@ -580,6 +569,7 @@ load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 
#

core-$(CONFIG_TOSHIBA_RBTX4927)	+= arch/mips/tx4927/toshiba_rbtx4927/

core-$(CONFIG_TOSHIBA_RBTX4927)	+= arch/mips/tx4927/common/

cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx

load-$(CONFIG_TOSHIBA_RBTX4927)	+= 0xffffffff80020000



#
@@ -587,6 +577,7 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 
#

core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/

core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/

cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx

load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000



cflags-y			+= -Iinclude/asm-mips/mach-generic
@@ -603,7 +594,8 @@ JIFFIES = jiffies_64 
endif



AFLAGS		+= $(cflags-y)

CFLAGS		+= $(cflags-y)

CFLAGS		+= $(cflags-y) \

			-D"VMLINUX_LOAD_ADDRESS=$(load-y)"



LDFLAGS			+= -m $(ld-emul)
@@ -633,18 +625,11 @@ CPPFLAGS_vmlinux.lds := \ 
head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o



libs-y			+= arch/mips/lib/

libs-$(CONFIG_32BIT)	+= arch/mips/lib-32/

libs-$(CONFIG_64BIT)	+= arch/mips/lib-64/



core-y			+= arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/



drivers-$(CONFIG_OPROFILE)	+= arch/mips/oprofile/



ifdef CONFIG_LASAT

rom.bin rom.sw: vmlinux

	$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@

endif



#

# Some machines like the Indy need 32-bit ELF binaries for booting purposes.

# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@@ -702,32 +687,19 @@ vmlinux.srec: $(vmlinux-32) 
CLEAN_FILES += vmlinux.ecoff \

	       vmlinux.srec



archprepare:

ifdef CONFIG_MIPS32_N32

	@echo '  Checking missing-syscalls for N32'

	$(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=n32"

endif

ifdef CONFIG_MIPS32_O32

	@echo '  Checking missing-syscalls for O32'

	$(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"

endif



archclean:

	@$(MAKE) $(clean)=arch/mips/boot

	@$(MAKE) $(clean)=arch/mips/lasat



CLEAN_FILES += vmlinux.32 \

	       vmlinux.64 \

	       vmlinux.ecoff
 


quiet_cmd_syscalls_n32 = CALL-N32 $<

      cmd_syscalls_n32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=n32



quiet_cmd_syscalls_o32 = CALL-O32 $<

      cmd_syscalls_o32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=32



PHONY += missing-syscalls-n32 missing-syscalls-o32



missing-syscalls-n32: scripts/checksyscalls.sh FORCE

	$(call cmd,syscalls_n32)



missing-syscalls-o32: scripts/checksyscalls.sh FORCE

	$(call cmd,syscalls_o32)



archprepare:

ifdef CONFIG_MIPS32_N32

	$(Q)$(MAKE) $(build)=arch/mips missing-syscalls-n32

endif

ifdef CONFIG_MIPS32_O32

	$(Q)$(MAKE) $(build)=arch/mips missing-syscalls-o32

endif

arch/mips/au1000/common/gpio.c

+81 −43
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>

 *  	Architecture specific GPIO support

 *

 *  This program is free software; you can redistribute	 it and/or modify it

 *  under  the terms of	 the GNU General  Public License as published by the

 *  Free Software Foundation;  either version 2 of the	License, or (at your
@@ -18,101 +21,136 @@ 
 *  You should have received a copy of the  GNU General Public License along

 *  with this program; if not, write  to the Free Software Foundation, Inc.,

 *  675 Mass Ave, Cambridge, MA 02139, USA.

 *

 *  Notes :

 * 	au1000 SoC have only one GPIO line : GPIO1

 * 	others have a second one : GPIO2

 */



#include <linux/autoconf.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/types.h>

#include <linux/module.h>

#include <au1000.h>

#include <au1xxx_gpio.h>



#include <asm/addrspace.h>



#include <asm/mach-au1x00/au1000.h>

#include <asm/gpio.h>



#define gpio1 sys

#if !defined(CONFIG_SOC_AU1000)

static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;



static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;

#define GPIO2_OUTPUT_ENABLE_MASK 	0x00010000



int au1xxx_gpio2_read(int signal)

static int au1xxx_gpio2_read(unsigned gpio)

{

	signal -= 200;

/*	gpio2->dir &= ~(0x01 << signal);						//Set GPIO to input */

	return ((gpio2->pinstate >> signal) & 0x01);

	gpio -= AU1XXX_GPIO_BASE;

	return ((gpio2->pinstate >> gpio) & 0x01);

}



void au1xxx_gpio2_write(int signal, int value)

static void au1xxx_gpio2_write(unsigned gpio, int value)

{

	signal -= 200;

	gpio -= AU1XXX_GPIO_BASE;



	gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);

}



	gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) |

		(value << signal);

static int au1xxx_gpio2_direction_input(unsigned gpio)

{

	gpio -= AU1XXX_GPIO_BASE;

	gpio2->dir &= ~(0x01 << gpio);

	return 0;

}



void au1xxx_gpio2_tristate(int signal)

static int au1xxx_gpio2_direction_output(unsigned gpio, int value)

{

	signal -= 200;

	gpio2->dir &= ~(0x01 << signal); 	/* Set GPIO to input */

	gpio -= AU1XXX_GPIO_BASE;

	gpio2->dir = (0x01 << gpio) | (value << gpio);

	return 0;

}

#endif



int au1xxx_gpio1_read(int signal)

#endif /* !defined(CONFIG_SOC_AU1000) */



static int au1xxx_gpio1_read(unsigned gpio)

{

/*	gpio1->trioutclr |= (0x01 << signal); */

	return ((gpio1->pinstaterd >> signal) & 0x01);

	return ((gpio1->pinstaterd >> gpio) & 0x01);

}



void au1xxx_gpio1_write(int signal, int value)

static void au1xxx_gpio1_write(unsigned gpio, int value)

{

	if (value)

		gpio1->outputset = (0x01 << signal);

		gpio1->outputset = (0x01 << gpio);

	else

		gpio1->outputclr = (0x01 << signal);	/* Output a Zero */

		/* Output a zero */

		gpio1->outputclr = (0x01 << gpio);

}



void au1xxx_gpio1_tristate(int signal)

static int au1xxx_gpio1_direction_input(unsigned gpio)

{

	gpio1->trioutclr = (0x01 << signal);		/* Tristate signal */

	gpio1->pininputen = (0x01 << gpio);

	return 0;

}



static int au1xxx_gpio1_direction_output(unsigned gpio, int value)

{

	gpio1->trioutclr = (0x01 & gpio);

	return 0;

}



int au1xxx_gpio_read(int signal)

int au1xxx_gpio_get_value(unsigned gpio)

{

	if(signal >= 200)

	if (gpio >= AU1XXX_GPIO_BASE)

#if defined(CONFIG_SOC_AU1000)

		return 0;

#else

		return au1xxx_gpio2_read(signal);

		return au1xxx_gpio2_read(gpio);

#endif

	else

		return au1xxx_gpio1_read(signal);

		return au1xxx_gpio1_read(gpio);

}



void au1xxx_gpio_write(int signal, int value)

EXPORT_SYMBOL(au1xxx_gpio_get_value);



void au1xxx_gpio_set_value(unsigned gpio, int value)

{

	if(signal >= 200)

	if (gpio >= AU1XXX_GPIO_BASE)

#if defined(CONFIG_SOC_AU1000)

		;

#else

		au1xxx_gpio2_write(signal, value);

		au1xxx_gpio2_write(gpio, value);

#endif

	else

		au1xxx_gpio1_write(signal, value);

		au1xxx_gpio1_write(gpio, value);

}



void au1xxx_gpio_tristate(int signal)

EXPORT_SYMBOL(au1xxx_gpio_set_value);



int au1xxx_gpio_direction_input(unsigned gpio)

{

	if(signal >= 200)

	if (gpio >= AU1XXX_GPIO_BASE)

#if defined(CONFIG_SOC_AU1000)

		;

#else

		au1xxx_gpio2_tristate(signal);

		return au1xxx_gpio2_direction_input(gpio);

#endif

	else

		au1xxx_gpio1_tristate(signal);

		return au1xxx_gpio1_direction_input(gpio);

}



void au1xxx_gpio1_set_inputs(void)

EXPORT_SYMBOL(au1xxx_gpio_direction_input);



int au1xxx_gpio_direction_output(unsigned gpio, int value)

{

	gpio1->pininputen = 0;

	if (gpio >= AU1XXX_GPIO_BASE)

#if defined(CONFIG_SOC_AU1000)

		;

#else

		return au1xxx_gpio2_direction_output(gpio, value);

#endif

	else

		return au1xxx_gpio1_direction_output(gpio, value);

}



EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);

EXPORT_SYMBOL(au1xxx_gpio_tristate);

EXPORT_SYMBOL(au1xxx_gpio_write);

EXPORT_SYMBOL(au1xxx_gpio_read);
 
EXPORT_SYMBOL(au1xxx_gpio_direction_output);

arch/mips/au1000/common/platform.c

+1 −1
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { 
#endif

};



int au1xxx_platform_init(void)

int __init au1xxx_platform_init(void)

{

	return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices));

}

arch/mips/configs/atlas_defconfig

+0 −4
Original line number Diff line number Diff line
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y 
# CONFIG_BASLER_EXCITE is not set

# CONFIG_MIPS_COBALT is not set

# CONFIG_MACH_DECSTATION is not set

# CONFIG_MIPS_EV64120 is not set

# CONFIG_MACH_JAZZ is not set

# CONFIG_LASAT is not set

CONFIG_MIPS_ATLAS=y

# CONFIG_MIPS_MALTA is not set

# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_MIPS_ATLAS=y 
# CONFIG_MIPS_SIM is not set

# CONFIG_MOMENCO_JAGUAR_ATX is not set

# CONFIG_MOMENCO_OCELOT is not set

# CONFIG_MOMENCO_OCELOT_3 is not set

# CONFIG_MOMENCO_OCELOT_C is not set

# CONFIG_MOMENCO_OCELOT_G is not set

# CONFIG_MIPS_XXS1500 is not set

# CONFIG_PNX8550_JBS is not set