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Commit 0ecebb9e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: switch to a finer grained reset for evergreen 



No change in functionality as we currently set all the reset
flags.

Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 71e3d157

drivers/gpu/drm/radeon/evergreen.c

+55 −25
Original line number Diff line number Diff line
@@ -2306,15 +2306,13 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin 
	return radeon_ring_test_lockup(rdev, ring);

}



static int evergreen_gpu_soft_reset(struct radeon_device *rdev)

static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)

{

	struct evergreen_mc_save save;

	u32 grbm_reset = 0, tmp;

	u32 grbm_reset = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return 0;

		return;



	dev_info(rdev->dev, "GPU softreset \n");

	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -2331,27 +2329,10 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);



	/* Disable DMA */

	tmp = RREG32(DMA_RB_CNTL);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	/* reset all the gfx blocks */

	grbm_reset = (SOFT_RESET_CP |

		      SOFT_RESET_CB |
@@ -2372,8 +2353,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
	udelay(50);

	WREG32(GRBM_SOFT_RESET, 0);

	(void)RREG32(GRBM_SOFT_RESET);

	/* Wait a little for things to settle down */

	udelay(50);



	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
@@ -2390,15 +2370,65 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

}



static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));



	/* Disable DMA */

	tmp = RREG32(DMA_RB_CNTL);

	tmp &= ~DMA_RB_ENABLE;

	WREG32(DMA_RB_CNTL, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

}



static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct evergreen_mc_save save;



	if (reset_mask == 0)

		return 0;



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		evergreen_gpu_soft_reset_gfx(rdev);



	if (reset_mask & RADEON_RESET_DMA)

		evergreen_gpu_soft_reset_dma(rdev);



	/* Wait a little for things to settle down */

	udelay(50);



	evergreen_mc_resume(rdev, &save);

	return 0;

}



int evergreen_asic_reset(struct radeon_device *rdev)

{

	return evergreen_gpu_soft_reset(rdev);

	return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					       RADEON_RESET_COMPUTE |

					       RADEON_RESET_DMA));

}



/* Interrupts */

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Diff line number Diff line
@@ -2037,5 +2037,6 @@ 
#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */

#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */

#define DMA_STATUS_REG                                    0xd034

#       define DMA_IDLE                                   (1 << 0)



#endif