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Commit 0ea5b2fd authored by Jacopo Mondi's avatar Jacopo Mondi Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77965: Add SCIF device nodes 



Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC.

Signed-off-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 838c1121

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+79 −6
Original line number Diff line number Diff line
@@ -335,27 +335,100 @@ 
		};



		scif0: serial@e6e60000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e60000 0 64>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 207>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,

			       <&dmac2 0x51>, <&dmac2 0x50>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 207>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 206>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,

			       <&dmac2 0x53>, <&dmac2 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 206>;

			status = "disabled";

		};



		scif2: serial@e6e88000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e88000 0 64>;

			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 310>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			power-domains = <&sysc 32>;

			resets = <&cpg 310>;

			status = "disabled";

		};



		scif3: serial@e6c50000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c50000 0 64>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 204>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x57>, <&dmac0 0x56>;

			dma-names = "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 204>;

			status = "disabled";

		};



		scif4: serial@e6c40000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c40000 0 64>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 203>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x59>, <&dmac0 0x58>;

			dma-names = "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 203>;

			status = "disabled";

		};



		scif5: serial@e6f30000 {

			/* placeholder */

			compatible = "renesas,scif-r8a77965",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6f30000 0 64>;

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 202>,

				 <&cpg CPG_CORE 20>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,

			       <&dmac2 0x5b>, <&dmac2 0x5a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 202>;

			status = "disabled";

		};



		avb: ethernet@e6800000 {