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Commit 0e72855e authored by Marc Zyngier's avatar Marc Zyngier Committed by Gerrit - the friendly Code Review server
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arm64: arch_timer: Add workaround for ARM erratum 1188873 



When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.

This only affects versions r0p0, r1p0 and r2p0 of the CPU.

Change-Id: If2026eff975725d41dc2f1630ab086f3cc7deea3
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Git-commit: 95b861a4a6d94f64d5242605569218160ebacdbe
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[neeraju@codeaurora: Resolve trivial merge conflicts.]
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 8deaf923

arch/arm64/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -494,6 +494,18 @@ config ARM64_ERRATUM_1024718 


	  If unsure, say Y.



config ARM64_ERRATUM_1188873

	bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	default y

	help

	  This option adds work arounds for ARM Cortex-A76 erratum 1188873



	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause

	  register corruption when accessing the timer registers from

	  AArch32 userspace.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -52,7 +52,8 @@ 
#define ARM64_MISMATCHED_CACHE_TYPE		31

#define ARM64_HAS_STAGE2_FWB			32

#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35



#define ARM64_NCAPS				35

#define ARM64_NCAPS				36



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define ARM_CPU_PART_CORTEX_A75		0xD0A

#define ARM_CPU_PART_CORTEX_A35		0xD04

#define ARM_CPU_PART_CORTEX_A55		0xD05

#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_KRYO5S		0x805



#define APM_CPU_PART_POTENZA		0x000
@@ -111,6 +112,7 @@ 
#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)

#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)

#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)

#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_KRYO5S	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO5S)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

arch/arm64/kernel/cpu_errata.c

+8 −0
Original line number Diff line number Diff line
@@ -701,6 +701,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = has_ssbd_mitigation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		/* Cortex-A76 r0p0 to r2p0 */

		.desc = "ARM erratum 1188873",

		.capability = ARM64_WORKAROUND_1188873,

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

	},

#endif

	{

	}

drivers/clocksource/arm_arch_timer.c

+14 −0
Original line number Diff line number Diff line
@@ -362,6 +362,12 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) 
	return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();

}

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

static u64 notrace arm64_1188873_read_cntvct_el0(void)

{

	return read_sysreg(cntvct_el0);

}

#endif



#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND

DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
@@ -465,6 +471,14 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { 
		.set_next_event_virt = erratum_set_next_event_tval_virt,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		.match_type = ate_match_local_cap_id,

		.id = (void *)ARM64_WORKAROUND_1188873,

		.desc = "ARM erratum 1188873",

		.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,

	},

#endif

};



typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,