wl1251: remove wl1251_ops (0e71bb08) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/net/wireless/wl12xx/Makefile

+1 −1

Original line number	Original line	Diff line number	Diff line
	wl1251-objs = wl1251_main.o wl1251_event.o \		wl1251-objs = wl1251_main.o wl1251_event.o \
	wl1251_tx.o wl1251_rx.o wl1251_ps.o wl1251_cmd.o \		wl1251_tx.o wl1251_rx.o wl1251_ps.o wl1251_cmd.o \
	wl1251_acx.o wl1251_boot.o wl1251_init.o \		wl1251_acx.o wl1251_boot.o wl1251_init.o \
	wl1251_ops.o wl1251_debugfs.o wl1251_io.o		wl1251_debugfs.o wl1251_io.o

	obj-$(CONFIG_WL1251) += wl1251.o		obj-$(CONFIG_WL1251) += wl1251.o
	obj-$(CONFIG_WL1251_SPI) += wl1251_spi.o		obj-$(CONFIG_WL1251_SPI) += wl1251_spi.o

drivers/net/wireless/wl12xx/wl1251.h

+18 −37

Original line number	Original line	Diff line number	Diff line
	@@ -143,35 +143,6 @@ struct wl1251_partition_set {

	struct wl1251;		struct wl1251;

	/* FIXME: I'm not sure about this structure name */
	struct wl1251_chip {
	u32 id;

	const char *fw_filename;
	const char *nvs_filename;

	char fw_ver[21];

	unsigned int power_on_sleep;
	int intr_cmd_complete;
	int intr_init_complete;

	int (op_upload_fw)(struct wl1251 wl);
	int (op_upload_nvs)(struct wl1251 wl);
	int (op_boot)(struct wl1251 wl);
	void (op_set_ecpu_ctrl)(struct wl1251 wl, u32 flag);
	void (op_target_enable_interrupts)(struct wl1251 wl);
	int (op_hw_init)(struct wl1251 wl);
	int (op_plt_init)(struct wl1251 wl);
	void (op_tx_flush)(struct wl1251 wl);
	void (op_fw_version)(struct wl1251 wl);
	int (op_cmd_join)(struct wl1251 wl, u8 bss_type, u8 dtim_interval,
	u16 beacon_interval, u8 wait);

	struct wl1251_partition_set *p_table;
	enum wl12xx_acx_int_reg *acx_reg_table;
	};

	struct wl1251_stats {		struct wl1251_stats {
	struct acx_statistics *fw_stats;		struct acx_statistics *fw_stats;
	unsigned long fw_stats_update;		unsigned long fw_stats_update;
	@@ -307,8 +278,6 @@ struct wl1251 {
	int virtual_mem_addr;		int virtual_mem_addr;
	int virtual_reg_addr;		int virtual_reg_addr;

	struct wl1251_chip chip;

	int cmd_box_addr;		int cmd_box_addr;
	int event_box_addr;		int event_box_addr;
	struct boot_attr boot_attr;		struct boot_attr boot_attr;
	@@ -401,6 +370,9 @@ struct wl1251 {
	u32 buffer_cmd;		u32 buffer_cmd;
	u8 buffer_busyword[WL1251_BUSY_WORD_LEN];		u8 buffer_busyword[WL1251_BUSY_WORD_LEN];
	struct wl1251_rx_descriptor *rx_descriptor;		struct wl1251_rx_descriptor *rx_descriptor;

			u32 chip_id;
			char fw_ver[21];
	};		};

	int wl1251_plt_start(struct wl1251 *wl);		int wl1251_plt_start(struct wl1251 *wl);
	@@ -420,16 +392,25 @@ void wl1251_disable_interrupts(struct wl1251 *wl);

	#define WL1251_TX_QUEUE_MAX_LENGTH 20		#define WL1251_TX_QUEUE_MAX_LENGTH 20

	/* Different chips need different sleep times after power on. WL1271 needs
	* 200ms, WL1251 needs only 10ms. By default we use 200ms, but as soon as we
	* know the chip ID, we change the sleep value in the wl1251 chip structure,
	* so in subsequent power ons, we don't waste more time then needed. */
	#define WL1251_DEFAULT_POWER_ON_SLEEP 200

	#define CHIP_ID_1251_PG10 (0x7010101)		#define CHIP_ID_1251_PG10 (0x7010101)
	#define CHIP_ID_1251_PG11 (0x7020101)		#define CHIP_ID_1251_PG11 (0x7020101)
	#define CHIP_ID_1251_PG12 (0x7030101)		#define CHIP_ID_1251_PG12 (0x7030101)
	#define CHIP_ID_1271_PG10 (0x4030101)		#define CHIP_ID_1271_PG10 (0x4030101)
	#define CHIP_ID_1271_PG20 (0x4030111)		#define CHIP_ID_1271_PG20 (0x4030111)

			#define WL1251_FW_NAME "wl1251-fw.bin"
			#define WL1251_NVS_NAME "wl1251-nvs.bin"

			#define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */

			#define WL1251_PART_DOWN_MEM_START 0x0
			#define WL1251_PART_DOWN_MEM_SIZE 0x16800
			#define WL1251_PART_DOWN_REG_START REGISTERS_BASE
			#define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE

			#define WL1251_PART_WORK_MEM_START 0x28000
			#define WL1251_PART_WORK_MEM_SIZE 0x14000
			#define WL1251_PART_WORK_REG_START REGISTERS_BASE
			#define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE

	#endif		#endif

drivers/net/wireless/wl12xx/wl1251_acx.c

+79 −0

Original line number	Original line	Diff line number	Diff line
	@@ -837,3 +837,82 @@ int wl1251_acx_statistics(struct wl1251 wl, struct acx_statistics stats)

	return 0;		return 0;
	}		}

			int wl1251_acx_rate_policies(struct wl1251 *wl)
			{
			struct acx_rate_policy *acx;
			int ret = 0;

			wl1251_debug(DEBUG_ACX, "acx rate policies");

			acx = kzalloc(sizeof(*acx), GFP_KERNEL);

			if (!acx) {
			ret = -ENOMEM;
			goto out;
			}

			/* configure one default (one-size-fits-all) rate class */
			acx->rate_class_cnt = 1;
			acx->rate_class[0].enabled_rates = ACX_RATE_MASK_UNSPECIFIED;
			acx->rate_class[0].short_retry_limit = ACX_RATE_RETRY_LIMIT;
			acx->rate_class[0].long_retry_limit = ACX_RATE_RETRY_LIMIT;
			acx->rate_class[0].aflags = 0;

			ret = wl1251_cmd_configure(wl, ACX_RATE_POLICY, acx, sizeof(*acx));
			if (ret < 0) {
			wl1251_warning("Setting of rate policies failed: %d", ret);
			goto out;
			}

			out:
			kfree(acx);
			return ret;
			}

			int wl1251_acx_mem_cfg(struct wl1251 *wl)
			{
			struct wl1251_acx_config_memory *mem_conf;
			int ret, i;

			wl1251_debug(DEBUG_ACX, "acx mem cfg");

			mem_conf = kzalloc(sizeof(*mem_conf), GFP_KERNEL);
			if (!mem_conf) {
			ret = -ENOMEM;
			goto out;
			}

			/* memory config */
			mem_conf->mem_config.num_stations = cpu_to_le16(DEFAULT_NUM_STATIONS);
			mem_conf->mem_config.rx_mem_block_num = 35;
			mem_conf->mem_config.tx_min_mem_block_num = 64;
			mem_conf->mem_config.num_tx_queues = MAX_TX_QUEUES;
			mem_conf->mem_config.host_if_options = HOSTIF_PKT_RING;
			mem_conf->mem_config.num_ssid_profiles = 1;
			mem_conf->mem_config.debug_buffer_size =
			cpu_to_le16(TRACE_BUFFER_MAX_SIZE);

			/* RX queue config */
			mem_conf->rx_queue_config.dma_address = 0;
			mem_conf->rx_queue_config.num_descs = ACX_RX_DESC_DEF;
			mem_conf->rx_queue_config.priority = DEFAULT_RXQ_PRIORITY;
			mem_conf->rx_queue_config.type = DEFAULT_RXQ_TYPE;

			/* TX queue config */
			for (i = 0; i < MAX_TX_QUEUES; i++) {
			mem_conf->tx_queue_config[i].num_descs = ACX_TX_DESC_DEF;
			mem_conf->tx_queue_config[i].attributes = i;
			}

			ret = wl1251_cmd_configure(wl, ACX_MEM_CFG, mem_conf,
			sizeof(*mem_conf));
			if (ret < 0) {
			wl1251_warning("wl1251 mem config failed: %d", ret);
			goto out;
			}

			out:
			kfree(mem_conf);
			return ret;
			}

drivers/net/wireless/wl12xx/wl1251_acx.h

+146 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1031,6 +1031,150 @@ struct acx_statistics {
	struct acx_rxpipe_statistics rxpipe;		struct acx_rxpipe_statistics rxpipe;
	} __attribute__ ((packed));		} __attribute__ ((packed));

			#define ACX_MAX_RATE_CLASSES 8
			#define ACX_RATE_MASK_UNSPECIFIED 0
			#define ACX_RATE_RETRY_LIMIT 10

			struct acx_rate_class {
			u32 enabled_rates;
			u8 short_retry_limit;
			u8 long_retry_limit;
			u8 aflags;
			u8 reserved;
			};

			struct acx_rate_policy {
			struct acx_header header;

			u32 rate_class_cnt;
			struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
			} __attribute__ ((packed));

			struct wl1251_acx_memory {
			__le16 num_stations; /* number of STAs to be supported. */
			u16 reserved_1;

			/*
			* Nmber of memory buffers for the RX mem pool.
			* The actual number may be less if there are
			* not enough blocks left for the minimum num
			* of TX ones.
			*/
			u8 rx_mem_block_num;
			u8 reserved_2;
			u8 num_tx_queues; /* From 1 to 16 */
			u8 host_if_options; /* HOST_IF* */
			u8 tx_min_mem_block_num;
			u8 num_ssid_profiles;
			__le16 debug_buffer_size;
			} __attribute__ ((packed));


			#define ACX_RX_DESC_MIN 1
			#define ACX_RX_DESC_MAX 127
			#define ACX_RX_DESC_DEF 32
			struct wl1251_acx_rx_queue_config {
			u8 num_descs;
			u8 pad;
			u8 type;
			u8 priority;
			__le32 dma_address;
			} __attribute__ ((packed));

			#define ACX_TX_DESC_MIN 1
			#define ACX_TX_DESC_MAX 127
			#define ACX_TX_DESC_DEF 16
			struct wl1251_acx_tx_queue_config {
			u8 num_descs;
			u8 pad[2];
			u8 attributes;
			} __attribute__ ((packed));

			#define MAX_TX_QUEUE_CONFIGS 5
			#define MAX_TX_QUEUES 4
			struct wl1251_acx_config_memory {
			struct acx_header header;

			struct wl1251_acx_memory mem_config;
			struct wl1251_acx_rx_queue_config rx_queue_config;
			struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS];
			} __attribute__ ((packed));

			struct wl1251_acx_mem_map {
			struct acx_header header;

			void *code_start;
			void *code_end;

			void *wep_defkey_start;
			void *wep_defkey_end;

			void *sta_table_start;
			void *sta_table_end;

			void *packet_template_start;
			void *packet_template_end;

			void *queue_memory_start;
			void *queue_memory_end;

			void *packet_memory_pool_start;
			void *packet_memory_pool_end;

			void *debug_buffer1_start;
			void *debug_buffer1_end;

			void *debug_buffer2_start;
			void *debug_buffer2_end;

			/* Number of blocks FW allocated for TX packets */
			u32 num_tx_mem_blocks;

			/* Number of blocks FW allocated for RX packets */
			u32 num_rx_mem_blocks;
			} __attribute__ ((packed));

			/*************************************************************************

			Host Interrupt Register (WiLink -> Host)

			**************************************************************************/

			/* RX packet is ready in Xfer buffer #0 */
			#define WL1251_ACX_INTR_RX0_DATA BIT(0)

			/* TX result(s) are in the TX complete buffer */
			#define WL1251_ACX_INTR_TX_RESULT BIT(1)

			/* OBSOLETE */
			#define WL1251_ACX_INTR_TX_XFR BIT(2)

			/* RX packet is ready in Xfer buffer #1 */
			#define WL1251_ACX_INTR_RX1_DATA BIT(3)

			/* Event was entered to Event MBOX #A */
			#define WL1251_ACX_INTR_EVENT_A BIT(4)

			/* Event was entered to Event MBOX #B */
			#define WL1251_ACX_INTR_EVENT_B BIT(5)

			/* OBSOLETE */
			#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6)

			/* Trace meassge on MBOX #A */
			#define WL1251_ACX_INTR_TRACE_A BIT(7)

			/* Trace meassge on MBOX #B */
			#define WL1251_ACX_INTR_TRACE_B BIT(8)

			/* Command processing completion */
			#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9)

			/* Init sequence is done */
			#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14)

			#define WL1251_ACX_INTR_ALL 0xFFFFFFFF

	enum {		enum {
	ACX_WAKE_UP_CONDITIONS = 0x0002,		ACX_WAKE_UP_CONDITIONS = 0x0002,
	ACX_MEM_CFG = 0x0003,		ACX_MEM_CFG = 0x0003,
	@@ -1142,5 +1286,7 @@ int wl1251_acx_cts_protect(struct wl1251 *wl,
	enum acx_ctsprotect_type ctsprotect);		enum acx_ctsprotect_type ctsprotect);
	int wl1251_acx_statistics(struct wl1251 wl, struct acx_statistics stats);		int wl1251_acx_statistics(struct wl1251 wl, struct acx_statistics stats);
	int wl1251_acx_tsf_info(struct wl1251 wl, u64 mactime);		int wl1251_acx_tsf_info(struct wl1251 wl, u64 mactime);
			int wl1251_acx_rate_policies(struct wl1251 *wl);
			int wl1251_acx_mem_cfg(struct wl1251 *wl);

	#endif /* __WL1251_ACX_H__ */		#endif /* __WL1251_ACX_H__ */

drivers/net/wireless/wl12xx/wl1251_boot.c

+245 −11

Original line number	Original line	Diff line number	Diff line
	@@ -28,6 +28,7 @@
	#include "wl1251_io.h"		#include "wl1251_io.h"
	#include "wl1251_spi.h"		#include "wl1251_spi.h"
	#include "wl1251_event.h"		#include "wl1251_event.h"
			#include "wl1251_acx.h"

	void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)		void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
	{		{
	@@ -208,18 +209,30 @@ int wl1251_boot_init_seq(struct wl1251 *wl)
	return 0;		return 0;
	}		}

			static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
			{
			u32 cpu_ctrl;

			/* 10.5.0 run the firmware (I) */
			cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

			/* 10.5.1 run the firmware (II) */
			cpu_ctrl &= ~flag;
			wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
			}

	int wl1251_boot_run_firmware(struct wl1251 *wl)		int wl1251_boot_run_firmware(struct wl1251 *wl)
	{		{
	int loop, ret;		int loop, ret;
	u32 chip_id, interrupt;		u32 chip_id, interrupt;

	wl->chip.op_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);		wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1251_reg_read32(wl, CHIP_ID_B);		chip_id = wl1251_reg_read32(wl, CHIP_ID_B);

	wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);		wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip.id) {		if (chip_id != wl->chip_id) {
	wl1251_error("chip id doesn't match after firmware boot");		wl1251_error("chip id doesn't match after firmware boot");
	return -EIO;		return -EIO;
	}		}
	@@ -236,9 +249,9 @@ int wl1251_boot_run_firmware(struct wl1251 *wl)
	return -EIO;		return -EIO;
	}		}
	/* check that ACX_INTR_INIT_COMPLETE is enabled */		/* check that ACX_INTR_INIT_COMPLETE is enabled */
	else if (interrupt & wl->chip.intr_init_complete) {		else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,		wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
	wl->chip.intr_init_complete);		WL1251_ACX_INTR_INIT_COMPLETE);
	break;		break;
	}		}
	}		}
	@@ -256,16 +269,15 @@ int wl1251_boot_run_firmware(struct wl1251 *wl)
	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);		wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */		/* set the working partition to its "running" mode offset */
	wl1251_set_partition(wl,		wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
	wl->chip.p_table[PART_WORK].mem.start,		WL1251_PART_WORK_MEM_SIZE,
	wl->chip.p_table[PART_WORK].mem.size,		WL1251_PART_WORK_REG_START,
	wl->chip.p_table[PART_WORK].reg.start,		WL1251_PART_WORK_REG_SIZE);
	wl->chip.p_table[PART_WORK].reg.size);

	wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",		wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
	wl->cmd_box_addr, wl->event_box_addr);		wl->cmd_box_addr, wl->event_box_addr);

	wl->chip.op_fw_version(wl);		wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));

	/*		/*
	* in case of full asynchronous mode the firmware event must be		* in case of full asynchronous mode the firmware event must be
	@@ -275,7 +287,14 @@ int wl1251_boot_run_firmware(struct wl1251 *wl)
	/* enable gpio interrupts */		/* enable gpio interrupts */
	wl1251_enable_interrupts(wl);		wl1251_enable_interrupts(wl);

	wl->chip.op_target_enable_interrupts(wl);		/* Enable target's interrupts */
			wl->intr_mask = WL1251_ACX_INTR_RX0_DATA \|
			WL1251_ACX_INTR_RX1_DATA \|
			WL1251_ACX_INTR_TX_RESULT \|
			WL1251_ACX_INTR_EVENT_A \|
			WL1251_ACX_INTR_EVENT_B \|
			WL1251_ACX_INTR_INIT_COMPLETE;
			wl1251_boot_target_enable_interrupts(wl);

	/* unmask all mbox events */		/* unmask all mbox events */
	wl->event_mask = 0xffffffff;		wl->event_mask = 0xffffffff;
	@@ -291,3 +310,218 @@ int wl1251_boot_run_firmware(struct wl1251 *wl)
	/* firmware startup completed */		/* firmware startup completed */
	return 0;		return 0;
	}		}

			static int wl1251_boot_upload_firmware(struct wl1251 *wl)
			{
			int addr, chunk_num, partition_limit;
			size_t fw_data_len;
			u8 *p;

			/* whal_FwCtrl_LoadFwImageSm() */

			wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
			wl1251_reg_read32(wl, CHIP_ID_B));

			/* 10.0 check firmware length and set partition */
			fw_data_len = (wl->fw[4] << 24) \| (wl->fw[5] << 16) \|
			(wl->fw[6] << 8) \| (wl->fw[7]);

			wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
			CHUNK_SIZE);

			if ((fw_data_len % 4) != 0) {
			wl1251_error("firmware length not multiple of four");
			return -EIO;
			}

			wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
			WL1251_PART_DOWN_MEM_SIZE,
			WL1251_PART_DOWN_REG_START,
			WL1251_PART_DOWN_REG_SIZE);

			/* 10.1 set partition limit and chunk num */
			chunk_num = 0;
			partition_limit = WL1251_PART_DOWN_MEM_SIZE;

			while (chunk_num < fw_data_len / CHUNK_SIZE) {
			/* 10.2 update partition, if needed */
			addr = WL1251_PART_DOWN_MEM_START +
			(chunk_num + 2) * CHUNK_SIZE;
			if (addr > partition_limit) {
			addr = WL1251_PART_DOWN_MEM_START +
			chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
			WL1251_PART_DOWN_MEM_SIZE;
			wl1251_set_partition(wl,
			addr,
			WL1251_PART_DOWN_MEM_SIZE,
			WL1251_PART_DOWN_REG_START,
			WL1251_PART_DOWN_REG_SIZE);
			}

			/* 10.3 upload the chunk */
			addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
			p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
			wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			p, addr);
			wl1251_mem_write(wl, addr, p, CHUNK_SIZE);

			chunk_num++;
			}

			/* 10.4 upload the last chunk */
			addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
			p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
			wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
			fw_data_len % CHUNK_SIZE, p, addr);
			wl1251_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);

			return 0;
			}

			static int wl1251_boot_upload_nvs(struct wl1251 *wl)
			{
			size_t nvs_len, nvs_bytes_written, burst_len;
			int nvs_start, i;
			u32 dest_addr, val;
			u8 nvs_ptr, nvs;

			nvs = wl->nvs;
			if (nvs == NULL)
			return -ENODEV;

			nvs_ptr = nvs;

			nvs_len = wl->nvs_len;
			nvs_start = wl->fw_len;

			/*
			* Layout before the actual NVS tables:
			* 1 byte : burst length.
			* 2 bytes: destination address.
			* n bytes: data to burst copy.
			*
			* This is ended by a 0 length, then the NVS tables.
			*/

			while (nvs_ptr[0]) {
			burst_len = nvs_ptr[0];
			dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));

			/* We move our pointer to the data */
			nvs_ptr += 3;

			for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
			\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));

			wl1251_debug(DEBUG_BOOT,
			"nvs burst write 0x%x: 0x%x",
			dest_addr, val);
			wl1251_mem_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
			}
			}

			/*
			* We've reached the first zero length, the first NVS table
			* is 7 bytes further.
			*/
			nvs_ptr += 7;
			nvs_len -= nvs_ptr - nvs;
			nvs_len = ALIGN(nvs_len, 4);

			/* Now we must set the partition correctly */
			wl1251_set_partition(wl, nvs_start,
			WL1251_PART_DOWN_MEM_SIZE,
			WL1251_PART_DOWN_REG_START,
			WL1251_PART_DOWN_REG_SIZE);

			/* And finally we upload the NVS tables */
			nvs_bytes_written = 0;
			while (nvs_bytes_written < nvs_len) {
			val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
			\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));

			val = cpu_to_le32(val);

			wl1251_debug(DEBUG_BOOT,
			"nvs write table 0x%x: 0x%x",
			nvs_start, val);
			wl1251_mem_write32(wl, nvs_start, val);

			nvs_ptr += 4;
			nvs_bytes_written += 4;
			nvs_start += 4;
			}

			return 0;
			}

			int wl1251_boot(struct wl1251 *wl)
			{
			int ret = 0, minor_minor_e2_ver;
			u32 tmp, boot_data;

			ret = wl1251_boot_soft_reset(wl);
			if (ret < 0)
			goto out;

			/* 2. start processing NVS file */
			ret = wl1251_boot_upload_nvs(wl);
			if (ret < 0)
			goto out;

			/* write firmware's last address (ie. it's length) to
			* ACX_EEPROMLESS_IND_REG */
			wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);

			/* 6. read the EEPROM parameters */
			tmp = wl1251_reg_read32(wl, SCR_PAD2);

			/* 7. read bootdata */
			wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
			wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
			tmp = wl1251_reg_read32(wl, SCR_PAD3);

			/* 8. check bootdata and call restart sequence */
			wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
			minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;

			wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
			"minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
			wl->boot_attr.radio_type, wl->boot_attr.major,
			wl->boot_attr.minor, minor_minor_e2_ver);

			ret = wl1251_boot_init_seq(wl);
			if (ret < 0)
			goto out;

			/* 9. NVS processing done */
			boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

			wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);

			/* 10. check that ECPU_CONTROL_HALT bits are set in
			* pWhalBus->uBootData and start uploading firmware
			*/
			if ((boot_data & ECPU_CONTROL_HALT) == 0) {
			wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
			ret = -EIO;
			goto out;
			}

			ret = wl1251_boot_upload_firmware(wl);
			if (ret < 0)
			goto out;

			/* 10.5 start firmware */
			ret = wl1251_boot_run_firmware(wl);
			if (ret < 0)
			goto out;

			out:
			return ret;
			}