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Commit 0e704476 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move common code out of i915_gpu_error.c 



In the next patch, I want to conditionally compile i915_gpu_error.c and
that requires moving the functions used by debug out of
i915_gpu_error.c!

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161012090522.367-1-chris@chris-wilson.co.uk
parent 40006c43

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -1339,7 +1339,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) 
		seqno[id] = intel_engine_get_seqno(engine);

	}



	i915_get_engine_instdone(dev_priv, RCS, &instdone);

	intel_engine_get_instdone(&dev_priv->engine[RCS], &instdone);



	intel_runtime_pm_put(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+0 −3
Original line number Diff line number Diff line
@@ -3564,9 +3564,6 @@ void i915_error_state_get(struct drm_device *dev, 
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);

void i915_destroy_error_state(struct drm_device *dev);



void i915_get_engine_instdone(struct drm_i915_private *dev_priv,

			      enum intel_engine_id engine_id,

			      struct intel_instdone *instdone);

const char *i915_cache_level_str(struct drm_i915_private *i915, int type);



/* i915_cmd_parser.c */

drivers/gpu/drm/i915/i915_gpu_error.c

+1 −105
Original line number Diff line number Diff line
@@ -1038,7 +1038,7 @@ static void error_record_engine_registers(struct drm_i915_error_state *error, 
		ee->ipehr = I915_READ(IPEHR);

	}



	i915_get_engine_instdone(dev_priv, engine->id, &ee->instdone);

	intel_engine_get_instdone(engine, &ee->instdone);



	ee->waiting = intel_engine_has_waiter(engine);

	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
@@ -1548,107 +1548,3 @@ void i915_destroy_error_state(struct drm_device *dev) 
	if (error)

		kref_put(&error->ref, i915_error_state_free);

}
 


const char *i915_cache_level_str(struct drm_i915_private *i915, int type)

{

	switch (type) {

	case I915_CACHE_NONE: return " uncached";

	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";

	case I915_CACHE_L3_LLC: return " L3+LLC";

	case I915_CACHE_WT: return " WT";

	default: return "";

	}

}



static inline uint32_t

read_subslice_reg(struct drm_i915_private *dev_priv, int slice,

		  int subslice, i915_reg_t reg)

{

	uint32_t mcr;

	uint32_t ret;

	enum forcewake_domains fw_domains;



	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,

						    FW_REG_READ);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,

						     GEN8_MCR_SELECTOR,

						     FW_REG_READ | FW_REG_WRITE);



	spin_lock_irq(&dev_priv->uncore.lock);

	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);



	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);

	/*

	 * The HW expects the slice and sublice selectors to be reset to 0

	 * after reading out the registers.

	 */

	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));

	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	ret = I915_READ_FW(reg);



	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

	spin_unlock_irq(&dev_priv->uncore.lock);



	return ret;

}



/* NB: please notice the memset */

void i915_get_engine_instdone(struct drm_i915_private *dev_priv,

			      enum intel_engine_id engine_id,

			      struct intel_instdone *instdone)

{

	u32 mmio_base = dev_priv->engine[engine_id].mmio_base;

	int slice;

	int subslice;



	memset(instdone, 0, sizeof(*instdone));



	switch (INTEL_GEN(dev_priv)) {

	default:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine_id != RCS)

			break;



		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);

		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

			instdone->sampler[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_SAMPLER_INSTDONE);

			instdone->row[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_ROW_INSTDONE);

		}

		break;

	case 7:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine_id != RCS)

			break;



		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);

		instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);

		instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);



		break;

	case 6:

	case 5:

	case 4:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine_id == RCS)

			/* HACK: Using the wrong struct member */

			instdone->slice_common = I915_READ(GEN4_INSTDONE1);

		break;

	case 3:

	case 2:

		instdone->instdone = I915_READ(GEN2_INSTDONE);

		break;

	}

}

drivers/gpu/drm/i915/i915_irq.c

+2 −2
Original line number Diff line number Diff line
@@ -2588,7 +2588,7 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv) 


	pr_err("render error detected, EIR: 0x%08x\n", eir);



	i915_get_engine_instdone(dev_priv, RCS, &instdone);

	intel_engine_get_instdone(&dev_priv->engine[RCS], &instdone);



	if (IS_G4X(dev_priv)) {

		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
@@ -3001,7 +3001,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine) 
	if (engine->id != RCS)

		return true;



	i915_get_engine_instdone(dev_priv, RCS, &instdone);

	intel_engine_get_instdone(engine, &instdone);



	/* There might be unstable subunit states even when

	 * actual head is not moving. Filter out the unstable ones by

drivers/gpu/drm/i915/intel_engine_cs.c

+104 −0
Original line number Diff line number Diff line
@@ -349,3 +349,107 @@ u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine) 


	return bbaddr;

}



const char *i915_cache_level_str(struct drm_i915_private *i915, int type)

{

	switch (type) {

	case I915_CACHE_NONE: return " uncached";

	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";

	case I915_CACHE_L3_LLC: return " L3+LLC";

	case I915_CACHE_WT: return " WT";

	default: return "";

	}

}



static inline uint32_t

read_subslice_reg(struct drm_i915_private *dev_priv, int slice,

		  int subslice, i915_reg_t reg)

{

	uint32_t mcr;

	uint32_t ret;

	enum forcewake_domains fw_domains;



	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,

						    FW_REG_READ);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,

						     GEN8_MCR_SELECTOR,

						     FW_REG_READ | FW_REG_WRITE);



	spin_lock_irq(&dev_priv->uncore.lock);

	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);



	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);

	/*

	 * The HW expects the slice and sublice selectors to be reset to 0

	 * after reading out the registers.

	 */

	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));

	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	ret = I915_READ_FW(reg);



	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);

	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);



	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);

	spin_unlock_irq(&dev_priv->uncore.lock);



	return ret;

}



/* NB: please notice the memset */

void intel_engine_get_instdone(struct intel_engine_cs *engine,

			       struct intel_instdone *instdone)

{

	struct drm_i915_private *dev_priv = engine->i915;

	u32 mmio_base = engine->mmio_base;

	int slice;

	int subslice;



	memset(instdone, 0, sizeof(*instdone));



	switch (INTEL_GEN(dev_priv)) {

	default:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine->id != RCS)

			break;



		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);

		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {

			instdone->sampler[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_SAMPLER_INSTDONE);

			instdone->row[slice][subslice] =

				read_subslice_reg(dev_priv, slice, subslice,

						  GEN7_ROW_INSTDONE);

		}

		break;

	case 7:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine->id != RCS)

			break;



		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);

		instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);

		instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);



		break;

	case 6:

	case 5:

	case 4:

		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));



		if (engine->id == RCS)

			/* HACK: Using the wrong struct member */

			instdone->slice_common = I915_READ(GEN4_INSTDONE1);

		break;

	case 3:

	case 2:

		instdone->instdone = I915_READ(GEN2_INSTDONE);

		break;

	}

}