Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0e5539b9 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge branch 'topic/ppgtt' into drm-intel-next-queued 



Because whatever.*

* This should contain a fairly long list of issues and still
unresolved resgressions, but I didn't really get a vote.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parents fc2c807b f72d21ed

drivers/gpu/drm/i915/i915_debugfs.c

+35 −5
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static const char *get_pin_flag(struct drm_i915_gem_object *obj) 
{

	if (obj->user_pin_count > 0)

		return "P";

	else if (obj->pin_count > 0)

	else if (i915_gem_obj_is_pinned(obj))

		return "p";

	else

		return " ";
@@ -123,6 +123,8 @@ static void 
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)

{

	struct i915_vma *vma;

	int pin_count = 0;



	seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",

		   &obj->base,

		   get_pin_flag(obj),
@@ -139,8 +141,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");

	if (obj->base.name)

		seq_printf(m, " (name: %d)", obj->base.name);

	if (obj->pin_count)

		seq_printf(m, " (pinned x %d)", obj->pin_count);

	list_for_each_entry(vma, &obj->vma_list, vma_link)

		if (vma->pin_count > 0)

			pin_count++;

		seq_printf(m, " (pinned x %d)", pin_count);

	if (obj->pin_display)

		seq_printf(m, " (display)");

	if (obj->fence_reg != I915_FENCE_REG_NONE)
@@ -447,7 +451,7 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data) 


	total_obj_size = total_gtt_size = count = 0;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {

		if (list == PINNED_LIST && obj->pin_count == 0)

		if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))

			continue;



		seq_puts(m, "   ");
@@ -1731,6 +1735,17 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
	return 0;

}



static int per_file_ctx(int id, void *ptr, void *data)

{

	struct i915_hw_context *ctx = ptr;

	struct seq_file *m = data;

	struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);



	ppgtt->debug_dump(ppgtt, m);



	return 0;

}



static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1760,6 +1775,7 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_ring_buffer *ring;

	struct drm_file *file;

	int i;



	if (INTEL_INFO(dev)->gen == 6)
@@ -1778,6 +1794,20 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 


		seq_puts(m, "aliasing PPGTT:\n");

		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);



		ppgtt->debug_dump(ppgtt, m);

	} else

		return;



	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct drm_i915_file_private *file_priv = file->driver_priv;

		struct i915_hw_ppgtt *pvt_ppgtt;



		pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);

		seq_printf(m, "proc: %s\n",

			   get_pid_task(file->pid, PIDTYPE_PID)->comm);

		seq_puts(m, "  default context:\n");

		idr_for_each(&file_priv->context_idr, per_file_ctx, m);

	}

	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));

}
@@ -2927,7 +2957,7 @@ i915_drop_caches_set(void *data, u64 val) 
		list_for_each_entry(vm, &dev_priv->vm_list, global_link) {

			list_for_each_entry_safe(vma, x, &vm->inactive_list,

						 mm_list) {

				if (vma->obj->pin_count)

				if (vma->pin_count)

					continue;



				ret = i915_vma_unbind(vma);

drivers/gpu/drm/i915/i915_dma.c

+3 −3
Original line number Diff line number Diff line
@@ -990,7 +990,7 @@ static int i915_getparam(struct drm_device *dev, void *data, 
		value = HAS_WT(dev);

		break;

	case I915_PARAM_HAS_ALIASING_PPGTT:

		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;

		value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);

		break;

	case I915_PARAM_HAS_WAIT_TIMEOUT:

		value = 1;
@@ -1374,7 +1374,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	i915_gem_cleanup_ringbuffer(dev);

	i915_gem_context_fini(dev);

	mutex_unlock(&dev->struct_mutex);

	i915_gem_cleanup_aliasing_ppgtt(dev);

	WARN_ON(dev_priv->mm.aliasing_ppgtt);

	drm_mm_takedown(&dev_priv->gtt.base.mm);

cleanup_power:

	intel_display_power_put(dev, POWER_DOMAIN_VGA);
@@ -1775,8 +1775,8 @@ int i915_driver_unload(struct drm_device *dev) 
		i915_gem_free_all_phys_object(dev);

		i915_gem_cleanup_ringbuffer(dev);

		i915_gem_context_fini(dev);

		WARN_ON(dev_priv->mm.aliasing_ppgtt);

		mutex_unlock(&dev->struct_mutex);

		i915_gem_cleanup_aliasing_ppgtt(dev);

		i915_gem_cleanup_stolen(dev);



		if (!I915_NEED_GFX_HWS(dev))

drivers/gpu/drm/i915/i915_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -113,7 +113,8 @@ MODULE_PARM_DESC(enable_hangcheck, 
int i915_enable_ppgtt __read_mostly = -1;

module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);

MODULE_PARM_DESC(i915_enable_ppgtt,

		"Enable PPGTT (default: true)");

		"Override PPGTT usage. "

		"(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");



int i915_enable_psr __read_mostly = 0;

module_param_named(enable_psr, i915_enable_psr, int, 0600);

drivers/gpu/drm/i915/i915_drv.h

+153 −73
Original line number Diff line number Diff line
@@ -523,6 +523,57 @@ enum i915_cache_level { 


typedef uint32_t gen6_gtt_pte_t;



/**

 * A VMA represents a GEM BO that is bound into an address space. Therefore, a

 * VMA's presence cannot be guaranteed before binding, or after unbinding the

 * object into/from the address space.

 *

 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime

 * will always be <= an objects lifetime. So object refcounting should cover us.

 */

struct i915_vma {

	struct drm_mm_node node;

	struct drm_i915_gem_object *obj;

	struct i915_address_space *vm;



	/** This object's place on the active/inactive lists */

	struct list_head mm_list;



	struct list_head vma_link; /* Link in the object's VMA list */



	/** This vma's place in the batchbuffer or on the eviction list */

	struct list_head exec_list;



	/**

	 * Used for performing relocations during execbuffer insertion.

	 */

	struct hlist_node exec_node;

	unsigned long exec_handle;

	struct drm_i915_gem_exec_object2 *exec_entry;



	/**

	 * How many users have pinned this object in GTT space. The following

	 * users can each hold at most one reference: pwrite/pread, pin_ioctl

	 * (via user_pin_count), execbuffer (objects are not allowed multiple

	 * times for the same batchbuffer), and the framebuffer code. When

	 * switching/pageflipping, the framebuffer code has at most two buffers

	 * pinned per crtc.

	 *

	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3

	 * bits with absolutely no headroom. So use 4 bits. */

	unsigned int pin_count:4;

#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf



	/** Unmap an object from an address space. This usually consists of

	 * setting the valid PTE entries to a reserved scratch page. */

	void (*unbind_vma)(struct i915_vma *vma);

	/* Map an object into an address space with the given cache flags. */

#define GLOBAL_BIND (1<<0)

	void (*bind_vma)(struct i915_vma *vma,

			 enum i915_cache_level cache_level,

			 u32 flags);

};



struct i915_address_space {

	struct drm_mm mm;

	struct drm_device *dev;
@@ -604,6 +655,8 @@ struct i915_gtt { 


struct i915_hw_ppgtt {

	struct i915_address_space base;

	struct kref ref;

	struct drm_mm_node node;

	unsigned num_pd_entries;

	union {

		struct page **pt_pages;
@@ -620,37 +673,12 @@ struct i915_hw_ppgtt { 
		dma_addr_t *pt_dma_addr;

		dma_addr_t *gen8_pt_dma_addr[4];

	};

	int (*enable)(struct drm_device *dev);

};



/**

 * A VMA represents a GEM BO that is bound into an address space. Therefore, a

 * VMA's presence cannot be guaranteed before binding, or after unbinding the

 * object into/from the address space.

 *

 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime

 * will always be <= an objects lifetime. So object refcounting should cover us.

 */

struct i915_vma {

	struct drm_mm_node node;

	struct drm_i915_gem_object *obj;

	struct i915_address_space *vm;



	/** This object's place on the active/inactive lists */

	struct list_head mm_list;



	struct list_head vma_link; /* Link in the object's VMA list */



	/** This vma's place in the batchbuffer or on the eviction list */

	struct list_head exec_list;



	/**

	 * Used for performing relocations during execbuffer insertion.

	 */

	struct hlist_node exec_node;

	unsigned long exec_handle;

	struct drm_i915_gem_exec_object2 *exec_entry;



	int (*enable)(struct i915_hw_ppgtt *ppgtt);

	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,

			 struct intel_ring_buffer *ring,

			 bool synchronous);

	void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);

};



struct i915_ctx_hang_stats {
@@ -675,9 +703,10 @@ struct i915_hw_context { 
	bool is_initialized;

	uint8_t remap_slice;

	struct drm_i915_file_private *file_priv;

	struct intel_ring_buffer *ring;

	struct intel_ring_buffer *last_ring;

	struct drm_i915_gem_object *obj;

	struct i915_ctx_hang_stats hang_stats;

	struct i915_address_space *vm;



	struct list_head link;

};
@@ -1622,18 +1651,6 @@ struct drm_i915_gem_object { 
	 */

	unsigned int fence_dirty:1;



	/** How many users have pinned this object in GTT space. The following

	 * users can each hold at most one reference: pwrite/pread, pin_ioctl

	 * (via user_pin_count), execbuffer (objects are not allowed multiple

	 * times for the same batchbuffer), and the framebuffer code. When

	 * switching/pageflipping, the framebuffer code has at most two buffers

	 * pinned per crtc.

	 *

	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3

	 * bits with absolutely no headroom. So use 4 bits. */

	unsigned int pin_count:4;

#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf



	/**

	 * Is the object at the current location in the gtt mappable and

	 * fenceable? Used to avoid costly recalculations.
@@ -1746,7 +1763,7 @@ struct drm_i915_file_private { 
	} mm;

	struct idr context_idr;



	struct i915_ctx_hang_stats hang_stats;

	struct i915_hw_context *private_default_ctx;

	atomic_t rps_wait_boost;

};
@@ -1820,6 +1837,9 @@ struct drm_i915_file_private { 


#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)

#define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))

#define HAS_PPGTT(dev)		(INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_BROADWELL(dev))

#define USES_ALIASING_PPGTT(dev) intel_enable_ppgtt(dev, false)

#define USES_FULL_PPGTT(dev)	intel_enable_ppgtt(dev, true)



#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)

#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
@@ -2000,6 +2020,8 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, 
			 const struct drm_i915_gem_object_ops *ops);

struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,

						  size_t size);

void i915_init_vm(struct drm_i915_private *dev_priv,

		  struct i915_address_space *vm);

void i915_gem_free_object(struct drm_gem_object *obj);

void i915_gem_vma_destroy(struct i915_vma *vma);
@@ -2008,7 +2030,7 @@ int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 
				     uint32_t alignment,

				     bool map_and_fenceable,

				     bool nonblocking);

void i915_gem_object_unpin(struct drm_i915_gem_object *obj);

void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);

int __must_check i915_vma_unbind(struct i915_vma *vma);

int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);

int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
@@ -2172,6 +2194,13 @@ i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 
				  struct i915_address_space *vm);



struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);

static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {

	struct i915_vma *vma;

	list_for_each_entry(vma, &obj->vma_list, vma_link)

		if (vma->pin_count > 0)

			return true;

	return false;

}



/* Some GGTT VM helpers */

#define obj_to_ggtt(obj) \
@@ -2211,46 +2240,51 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 
}



/* i915_gem_context.c */

#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)

int __must_check i915_gem_context_init(struct drm_device *dev);

void i915_gem_context_fini(struct drm_device *dev);

void i915_gem_context_reset(struct drm_device *dev);

int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);

int i915_gem_context_enable(struct drm_i915_private *dev_priv);

void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);

int i915_switch_context(struct intel_ring_buffer *ring,

			struct drm_file *file, int to_id);

			struct drm_file *file, struct i915_hw_context *to);

struct i915_hw_context *

i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);

void i915_gem_context_free(struct kref *ctx_ref);

static inline void i915_gem_context_reference(struct i915_hw_context *ctx)

{

	if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))

		kref_get(&ctx->ref);

}



static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)

{

	if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))

		kref_put(&ctx->ref, i915_gem_context_free);

}



struct i915_ctx_hang_stats * __must_check

i915_gem_context_get_hang_stats(struct drm_device *dev,

				struct drm_file *file,

				u32 id);

int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,

				  struct drm_file *file);

int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,

				   struct drm_file *file);



/* i915_gem_gtt.c */

void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);

void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,

			    struct drm_i915_gem_object *obj,

			    enum i915_cache_level cache_level);

void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,

			      struct drm_i915_gem_object *obj);

/* i915_gem_evict.c */

int __must_check i915_gem_evict_something(struct drm_device *dev,

					  struct i915_address_space *vm,

					  int min_size,

					  unsigned alignment,

					  unsigned cache_level,

					  bool mappable,

					  bool nonblock);

int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);

int i915_gem_evict_everything(struct drm_device *dev);



/* i915_gem_gtt.c */

void i915_check_and_clear_faults(struct drm_device *dev);

void i915_gem_suspend_gtt_mappings(struct drm_device *dev);

void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);

void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,

				enum i915_cache_level cache_level);

void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);

void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);

void i915_gem_init_global_gtt(struct drm_device *dev);

void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
@@ -2261,18 +2295,64 @@ static inline void i915_gem_chipset_flush(struct drm_device *dev) 
	if (INTEL_INFO(dev)->gen < 6)

		intel_gtt_chipset_flush();

}

int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);

static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)

{

	if (i915_enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))

		return false;



	if (i915_enable_ppgtt == 1 && full)

		return false;



/* i915_gem_evict.c */

int __must_check i915_gem_evict_something(struct drm_device *dev,

					  struct i915_address_space *vm,

					  int min_size,

					  unsigned alignment,

					  unsigned cache_level,

					  bool mappable,

					  bool nonblock);

int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);

int i915_gem_evict_everything(struct drm_device *dev);

#ifdef CONFIG_INTEL_IOMMU

	/* Disable ppgtt on SNB if VT-d is on. */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {

		DRM_INFO("Disabling PPGTT because VT-d is on\n");

		return false;

	}

#endif



	if (full)

		return HAS_PPGTT(dev);

	else

		return HAS_ALIASING_PPGTT(dev);

}



static inline void ppgtt_release(struct kref *kref)

{

	struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref);

	struct drm_device *dev = ppgtt->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct i915_address_space *vm = &ppgtt->base;



	if (ppgtt == dev_priv->mm.aliasing_ppgtt ||

	    (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {

		ppgtt->base.cleanup(&ppgtt->base);

		return;

	}



	/*

	 * Make sure vmas are unbound before we take down the drm_mm

	 *

	 * FIXME: Proper refcounting should take care of this, this shouldn't be

	 * needed at all.

	 */

	if (!list_empty(&vm->active_list)) {

		struct i915_vma *vma;



		list_for_each_entry(vma, &vm->active_list, mm_list)

			if (WARN_ON(list_empty(&vma->vma_link) ||

				    list_is_singular(&vma->vma_link)))

				break;



		i915_gem_evict_vm(&ppgtt->base, true);

	} else {

		i915_gem_retire_requests(dev);

		i915_gem_evict_vm(&ppgtt->base, false);

	}



	ppgtt->base.cleanup(&ppgtt->base);

}



/* i915_gem_stolen.c */

int i915_gem_init_stolen(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+105 −131

File changed.

Preview size limit exceeded, changes collapsed.