Merge "clk: qcom: camcc-kona: Enable CFA mode to lock CAM_CC PLL2 properly" (0e21d8db) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/camcc-kona.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -280,6 +280,9 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
		.config_ctl_val = 0x08200920,
		.config_ctl_hi_val = 0x05008011,
		.config_ctl_hi1_val = 0x00000000,
		.test_ctl_val = 0x00010000,
		.test_ctl_hi_val = 0x00000000,
		.test_ctl_hi1_val = 0x00000000,
		.user_ctl_val = 0x00000100,
		.user_ctl_hi_val = 0x00000000,
		.user_ctl_hi1_val = 0x00000000,

drivers/clk/qcom/clk-alpha-pll.c

+27 −6

Original line number	Diff line number	Diff line
		@@ -161,7 +161,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

		/* ZONDA PLL specific offsets */
		#define ZONDA_PLL_OUT_MASK 0x9

		#define ZONDA_STAY_IN_CFA BIT(16)
		#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)

		#define pll_alpha_width(p) \
		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
		@@ -216,6 +217,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
		#define wait_for_pll_enable_lock(pll) \
		wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")

		#define wait_for_zonda_pll_freq_lock(pll) \
		wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")

		#define wait_for_pll_disable(pll) \
		wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")

		@@ -879,8 +883,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		config->test_ctl_hi1_val);

		regmap_update_bits(regmap, PLL_MODE(pll),
		PLL_UPDATE_BYPASS,
		PLL_UPDATE_BYPASS);
		PLL_BYPASSNL, 0);

		/* Disable PLL output */
		regmap_update_bits(regmap, PLL_MODE(pll),
		@@ -900,7 +903,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		static int clk_zonda_pll_enable(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val;
		u32 val, test_ctl_val;
		int ret;

		ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
		@@ -937,6 +940,14 @@ static int clk_zonda_pll_enable(struct clk_hw *hw)
		regmap_write(pll->clkr.regmap, PLL_OPMODE(pll),
		PLL_OPMODE_RUN);

		ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
		if (ret)
		return ret;

		/* If cfa mode then poll for freq lock */
		if (test_ctl_val & ZONDA_STAY_IN_CFA)
		ret = wait_for_zonda_pll_freq_lock(pll);
		else
		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;
		@@ -1001,6 +1012,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		unsigned long rrate;
		u32 test_ctl_val;
		u32 l;
		u64 a;
		int ret;
		@@ -1022,6 +1034,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		/* Wait before polling for the frequency latch */
		udelay(5);

		/* Read stay in cfa mode */
		ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
		if (ret)
		return ret;

		/* If cfa mode then poll for freq lock */
		if (test_ctl_val & ZONDA_STAY_IN_CFA)
		ret = wait_for_zonda_pll_freq_lock(pll);
		else
		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;