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Commit 0dc46106 authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Do not do TLB pre-filling any more. 



In order to do it correctly on UltraSPARC-III+ and later we'd
need to add some complicated code to set the TAG access extension
register before loading the TLB.

Since this optimization gives questionable gains, it's best to
just remove it for now instead of adding the fix for Ultra-III+

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c5bd50a9

arch/sparc64/mm/init.c

+0 −6
Original line number Original line Diff line number Diff line
@@ -171,8 +171,6 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c 
			     : "g1", "g7");

			     : "g1", "g7");

}

}





extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);



void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)

void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)

{

{

	struct page *page;

	struct page *page;
@@ -199,10 +197,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p 




		put_cpu();

		put_cpu();

	}

	}



	if (get_thread_fault_code())

		__update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),

				   address, pte, get_thread_fault_code());

}

}





void flush_dcache_page(struct page *page)

void flush_dcache_page(struct page *page)

arch/sparc64/mm/ultra.S

+0 −29
Original line number Original line Diff line number Diff line
@@ -180,35 +180,6 @@ __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ 




	.previous

	.previous





	.align		32

__prefill_dtlb:

	rdpr		%pstate, %g7

	wrpr		%g7, PSTATE_IE, %pstate

	mov		TLB_TAG_ACCESS, %g1

	stxa		%o5, [%g1] ASI_DMMU

	stxa		%o2, [%g0] ASI_DTLB_DATA_IN

	flush		%g6

	retl

	 wrpr		%g7, %pstate

__prefill_itlb:

	rdpr		%pstate, %g7

	wrpr		%g7, PSTATE_IE, %pstate

	mov		TLB_TAG_ACCESS, %g1

	stxa		%o5, [%g1] ASI_IMMU

	stxa		%o2, [%g0] ASI_ITLB_DATA_IN

	flush		%g6

	retl

	 wrpr		%g7, %pstate



	.globl		__update_mmu_cache

__update_mmu_cache:	/* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */

	srlx		%o1, PAGE_SHIFT, %o1

	andcc		%o3, FAULT_CODE_DTLB, %g0

	sllx		%o1, PAGE_SHIFT, %o5

	bne,pt		%xcc, __prefill_dtlb

	 or		%o5, %o0, %o5

	ba,a,pt		%xcc, __prefill_itlb



	/* Cheetah specific versions, patched at boot time. */

	/* Cheetah specific versions, patched at boot time. */

__cheetah_flush_tlb_mm: /* 18 insns */

__cheetah_flush_tlb_mm: /* 18 insns */

	rdpr		%pstate, %g7

	rdpr		%pstate, %g7