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Commit 0d7b6b11 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915/chv: fix HW readout of the port PLL fractional divider 



Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional divider was always enabled. This may
result in a port clock state check mismatch if the preceeding modeset
disabled the fractional divider, but left a non-zero divider value in
the register.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d770e558

drivers/gpu/drm/i915/intel_display.c

+5 −2
Original line number Diff line number Diff line
@@ -7887,7 +7887,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, 
	int pipe = pipe_config->cpu_transcoder;

	enum dpio_channel port = vlv_pipe_to_channel(pipe);

	intel_clock_t clock;

	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;

	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;

	int refclk = 100000;



	mutex_lock(&dev_priv->sb_lock);
@@ -7895,10 +7895,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, 
	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));

	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));

	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));

	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));

	mutex_unlock(&dev_priv->sb_lock);



	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);

	clock.m2 = (pll_dw0 & 0xff) << 22;

	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)

		clock.m2 |= pll_dw2 & 0x3fffff;

	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;

	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;

	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;