Merge branch spi-next from git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git (0d73299d) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/spi/Kconfig

+12 −1

Original line number	Diff line number	Diff line
		@@ -297,9 +297,20 @@ config SPI_PPC4xx
		help
		This selects a driver for the PPC4xx SPI Controller.

		config SPI_PXA2XX_PXADMA
		bool "PXA2xx SSP legacy PXA DMA API support"
		depends on SPI_PXA2XX && ARCH_PXA
		help
		Enable PXA private legacy DMA API support. Note that this is
		deprecated in favor of generic DMA engine API.

		config SPI_PXA2XX_DMA
		def_bool y
		depends on SPI_PXA2XX && !SPI_PXA2XX_PXADMA

		config SPI_PXA2XX
		tristate "PXA2xx SSP SPI master"
		depends on ARCH_PXA \|\| PCI
		depends on ARCH_PXA \|\| PCI \|\| ACPI
		select PXA_SSP if ARCH_PXA
		help
		This enables using a PXA2xx or Sodaville SSP port as a SPI master

drivers/spi/Makefile

+4 −1

Original line number	Diff line number	Diff line
		@@ -47,7 +47,10 @@ obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
		obj-$(CONFIG_SPI_ORION) += spi-orion.o
		obj-$(CONFIG_SPI_PL022) += spi-pl022.o
		obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
		obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
		spi-pxa2xx-platform-objs := spi-pxa2xx.o
		spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
		spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
		obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
		obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
		obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
		obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o

drivers/spi/spi-pxa2xx-dma.c

0 → 100644

+392 −0

Original line number	Diff line number	Diff line
		/*
		* PXA2xx SPI DMA engine support.
		*
		* Copyright (C) 2013, Intel Corporation
		* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#include <linux/init.h>
		#include <linux/device.h>
		#include <linux/dma-mapping.h>
		#include <linux/dmaengine.h>
		#include <linux/pxa2xx_ssp.h>
		#include <linux/scatterlist.h>
		#include <linux/sizes.h>
		#include <linux/spi/spi.h>
		#include <linux/spi/pxa2xx_spi.h>

		#include "spi-pxa2xx.h"

		static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data,
		enum dma_data_direction dir)
		{
		int i, nents, len = drv_data->len;
		struct scatterlist *sg;
		struct device *dmadev;
		struct sg_table *sgt;
		void buf, pbuf;

		/*
		* Some DMA controllers have problems transferring buffers that are
		* not multiple of 4 bytes. So we truncate the transfer so that it
		* is suitable for such controllers, and handle the trailing bytes
		* manually after the DMA completes.
		*
		* REVISIT: It would be better if this information could be
		* retrieved directly from the DMA device in a similar way than
		* ->copy_align etc. is done.
		*/
		len = ALIGN(drv_data->len, 4);

		if (dir == DMA_TO_DEVICE) {
		dmadev = drv_data->tx_chan->device->dev;
		sgt = &drv_data->tx_sgt;
		buf = drv_data->tx;
		drv_data->tx_map_len = len;
		} else {
		dmadev = drv_data->rx_chan->device->dev;
		sgt = &drv_data->rx_sgt;
		buf = drv_data->rx;
		drv_data->rx_map_len = len;
		}

		nents = DIV_ROUND_UP(len, SZ_2K);
		if (nents != sgt->nents) {
		int ret;

		sg_free_table(sgt);
		ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
		if (ret)
		return ret;
		}

		pbuf = buf;
		for_each_sg(sgt->sgl, sg, sgt->nents, i) {
		size_t bytes = min_t(size_t, len, SZ_2K);

		if (buf)
		sg_set_buf(sg, pbuf, bytes);
		else
		sg_set_buf(sg, drv_data->dummy, bytes);

		pbuf += bytes;
		len -= bytes;
		}

		nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir);
		if (!nents)
		return -ENOMEM;

		return nents;
		}

		static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data,
		enum dma_data_direction dir)
		{
		struct device *dmadev;
		struct sg_table *sgt;

		if (dir == DMA_TO_DEVICE) {
		dmadev = drv_data->tx_chan->device->dev;
		sgt = &drv_data->tx_sgt;
		} else {
		dmadev = drv_data->rx_chan->device->dev;
		sgt = &drv_data->rx_sgt;
		}

		dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir);
		}

		static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
		{
		if (!drv_data->dma_mapped)
		return;

		pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE);
		pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);

		drv_data->dma_mapped = 0;
		}

		static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
		bool error)
		{
		struct spi_message *msg = drv_data->cur_msg;

		/*
		* It is possible that one CPU is handling ROR interrupt and other
		* just gets DMA completion. Calling pump_transfers() twice for the
		* same transfer leads to problems thus we prevent concurrent calls
		* by using ->dma_running.
		*/
		if (atomic_dec_and_test(&drv_data->dma_running)) {
		void __iomem *reg = drv_data->ioaddr;

		/*
		* If the other CPU is still handling the ROR interrupt we
		* might not know about the error yet. So we re-check the
		* ROR bit here before we clear the status register.
		*/
		if (!error) {
		u32 status = read_SSSR(reg) & drv_data->mask_sr;
		error = status & SSSR_ROR;
		}

		/* Clear status & disable interrupts */
		write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
		write_SSSR_CS(drv_data, drv_data->clear_sr);
		if (!pxa25x_ssp_comp(drv_data))
		write_SSTO(0, reg);

		if (!error) {
		pxa2xx_spi_unmap_dma_buffers(drv_data);

		/* Handle the last bytes of unaligned transfer */
		drv_data->tx += drv_data->tx_map_len;
		drv_data->write(drv_data);

		drv_data->rx += drv_data->rx_map_len;
		drv_data->read(drv_data);

		msg->actual_length += drv_data->len;
		msg->state = pxa2xx_spi_next_transfer(drv_data);
		} else {
		/* In case we got an error we disable the SSP now */
		write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

		msg->state = ERROR_STATE;
		}

		tasklet_schedule(&drv_data->pump_transfers);
		}
		}

		static void pxa2xx_spi_dma_callback(void *data)
		{
		pxa2xx_spi_dma_transfer_complete(data, false);
		}

		static struct dma_async_tx_descriptor *
		pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
		enum dma_transfer_direction dir)
		{
		struct pxa2xx_spi_master *pdata = drv_data->master_info;
		struct chip_data *chip = drv_data->cur_chip;
		enum dma_slave_buswidth width;
		struct dma_slave_config cfg;
		struct dma_chan *chan;
		struct sg_table *sgt;
		int nents, ret;

		switch (drv_data->n_bytes) {
		case 1:
		width = DMA_SLAVE_BUSWIDTH_1_BYTE;
		break;
		case 2:
		width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		break;
		default:
		width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		break;
		}

		memset(&cfg, 0, sizeof(cfg));
		cfg.direction = dir;

		if (dir == DMA_MEM_TO_DEV) {
		cfg.dst_addr = drv_data->ssdr_physical;
		cfg.dst_addr_width = width;
		cfg.dst_maxburst = chip->dma_burst_size;
		cfg.slave_id = pdata->tx_slave_id;

		sgt = &drv_data->tx_sgt;
		nents = drv_data->tx_nents;
		chan = drv_data->tx_chan;
		} else {
		cfg.src_addr = drv_data->ssdr_physical;
		cfg.src_addr_width = width;
		cfg.src_maxburst = chip->dma_burst_size;
		cfg.slave_id = pdata->rx_slave_id;

		sgt = &drv_data->rx_sgt;
		nents = drv_data->rx_nents;
		chan = drv_data->rx_chan;
		}

		ret = dmaengine_slave_config(chan, &cfg);
		if (ret) {
		dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
		return NULL;
		}

		return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir,
		DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
		}

		static bool pxa2xx_spi_dma_filter(struct dma_chan chan, void param)
		{
		const struct pxa2xx_spi_master *pdata = param;

		return chan->chan_id == pdata->tx_chan_id \|\|
		chan->chan_id == pdata->rx_chan_id;
		}

		bool pxa2xx_spi_dma_is_possible(size_t len)
		{
		return len <= MAX_DMA_LEN;
		}

		int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
		{
		const struct chip_data *chip = drv_data->cur_chip;
		int ret;

		if (!chip->enable_dma)
		return 0;

		/* Don't bother with DMA if we can't do even a single burst */
		if (drv_data->len < chip->dma_burst_size)
		return 0;

		ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE);
		if (ret <= 0) {
		dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n");
		return 0;
		}

		drv_data->tx_nents = ret;

		ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE);
		if (ret <= 0) {
		pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
		dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n");
		return 0;
		}

		drv_data->rx_nents = ret;
		return 1;
		}

		irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
		{
		u32 status;

		status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr;
		if (status & SSSR_ROR) {
		dev_err(&drv_data->pdev->dev, "FIFO overrun\n");

		dmaengine_terminate_all(drv_data->rx_chan);
		dmaengine_terminate_all(drv_data->tx_chan);

		pxa2xx_spi_dma_transfer_complete(drv_data, true);
		return IRQ_HANDLED;
		}

		return IRQ_NONE;
		}

		int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
		{
		struct dma_async_tx_descriptor tx_desc, rx_desc;

		tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
		if (!tx_desc) {
		dev_err(&drv_data->pdev->dev,
		"failed to get DMA TX descriptor\n");
		return -EBUSY;
		}

		rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
		if (!rx_desc) {
		dev_err(&drv_data->pdev->dev,
		"failed to get DMA RX descriptor\n");
		return -EBUSY;
		}

		/* We are ready when RX completes */
		rx_desc->callback = pxa2xx_spi_dma_callback;
		rx_desc->callback_param = drv_data;

		dmaengine_submit(rx_desc);
		dmaengine_submit(tx_desc);
		return 0;
		}

		void pxa2xx_spi_dma_start(struct driver_data *drv_data)
		{
		dma_async_issue_pending(drv_data->rx_chan);
		dma_async_issue_pending(drv_data->tx_chan);

		atomic_set(&drv_data->dma_running, 1);
		}

		int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
		{
		struct pxa2xx_spi_master *pdata = drv_data->master_info;
		dma_cap_mask_t mask;

		dma_cap_zero(mask);
		dma_cap_set(DMA_SLAVE, mask);

		drv_data->dummy = devm_kzalloc(&drv_data->pdev->dev, SZ_2K, GFP_KERNEL);
		if (!drv_data->dummy)
		return -ENOMEM;

		drv_data->tx_chan = dma_request_channel(mask, pxa2xx_spi_dma_filter,
		pdata);
		if (!drv_data->tx_chan)
		return -ENODEV;

		drv_data->rx_chan = dma_request_channel(mask, pxa2xx_spi_dma_filter,
		pdata);
		if (!drv_data->rx_chan) {
		dma_release_channel(drv_data->tx_chan);
		drv_data->tx_chan = NULL;
		return -ENODEV;
		}

		return 0;
		}

		void pxa2xx_spi_dma_release(struct driver_data *drv_data)
		{
		if (drv_data->rx_chan) {
		dmaengine_terminate_all(drv_data->rx_chan);
		dma_release_channel(drv_data->rx_chan);
		sg_free_table(&drv_data->rx_sgt);
		drv_data->rx_chan = NULL;
		}
		if (drv_data->tx_chan) {
		dmaengine_terminate_all(drv_data->tx_chan);
		dma_release_channel(drv_data->tx_chan);
		sg_free_table(&drv_data->tx_sgt);
		drv_data->tx_chan = NULL;
		}
		}

		void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
		{
		}

		int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
		struct spi_device *spi,
		u8 bits_per_word, u32 *burst_code,
		u32 *threshold)
		{
		struct pxa2xx_spi_chip *chip_info = spi->controller_data;

		/*
		* If the DMA burst size is given in chip_info we use that,
		* otherwise we use the default. Also we use the default FIFO
		* thresholds for now.
		*/
		*burst_code = chip_info ? chip_info->dma_burst_size : 16;
		*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
		\| SSCR1_TxTresh(TX_THRESH_DFLT);

		return 0;
		}

drivers/spi/spi-pxa2xx-pxadma.c

0 → 100644

+490 −0

Original line number	Diff line number	Diff line
		/*
		* PXA2xx SPI private DMA support.
		*
		* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
		*/

		#include <linux/init.h>
		#include <linux/delay.h>
		#include <linux/device.h>
		#include <linux/dma-mapping.h>
		#include <linux/pxa2xx_ssp.h>
		#include <linux/spi/spi.h>
		#include <linux/spi/pxa2xx_spi.h>

		#include "spi-pxa2xx.h"

		#define DMA_INT_MASK (DCSR_ENDINTR \| DCSR_STARTINTR \| DCSR_BUSERR)
		#define RESET_DMA_CHANNEL (DCSR_NODESC \| DMA_INT_MASK)

		bool pxa2xx_spi_dma_is_possible(size_t len)
		{
		/* Try to map dma buffer and do a dma transfer if successful, but
		* only if the length is non-zero and less than MAX_DMA_LEN.
		*
		* Zero-length non-descriptor DMA is illegal on PXA2xx; force use
		* of PIO instead. Care is needed above because the transfer may
		* have have been passed with buffers that are already dma mapped.
		* A zero-length transfer in PIO mode will not try to write/read
		* to/from the buffers
		*
		* REVISIT large transfers are exactly where we most want to be
		* using DMA. If this happens much, split those transfers into
		* multiple DMA segments rather than forcing PIO.
		*/
		return len > 0 && len <= MAX_DMA_LEN;
		}

		int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
		{
		struct spi_message *msg = drv_data->cur_msg;
		struct device *dev = &msg->spi->dev;

		if (!drv_data->cur_chip->enable_dma)
		return 0;

		if (msg->is_dma_mapped)
		return drv_data->rx_dma && drv_data->tx_dma;

		if (!IS_DMA_ALIGNED(drv_data->rx) \|\| !IS_DMA_ALIGNED(drv_data->tx))
		return 0;

		/* Modify setup if rx buffer is null */
		if (drv_data->rx == NULL) {
		*drv_data->null_dma_buf = 0;
		drv_data->rx = drv_data->null_dma_buf;
		drv_data->rx_map_len = 4;
		} else
		drv_data->rx_map_len = drv_data->len;


		/* Modify setup if tx buffer is null */
		if (drv_data->tx == NULL) {
		*drv_data->null_dma_buf = 0;
		drv_data->tx = drv_data->null_dma_buf;
		drv_data->tx_map_len = 4;
		} else
		drv_data->tx_map_len = drv_data->len;

		/* Stream map the tx buffer. Always do DMA_TO_DEVICE first
		* so we flush the cache before invalidating it, in case
		* the tx and rx buffers overlap.
		*/
		drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
		drv_data->tx_map_len, DMA_TO_DEVICE);
		if (dma_mapping_error(dev, drv_data->tx_dma))
		return 0;

		/* Stream map the rx buffer */
		drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
		drv_data->rx_map_len, DMA_FROM_DEVICE);
		if (dma_mapping_error(dev, drv_data->rx_dma)) {
		dma_unmap_single(dev, drv_data->tx_dma,
		drv_data->tx_map_len, DMA_TO_DEVICE);
		return 0;
		}

		return 1;
		}

		static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
		{
		struct device *dev;

		if (!drv_data->dma_mapped)
		return;

		if (!drv_data->cur_msg->is_dma_mapped) {
		dev = &drv_data->cur_msg->spi->dev;
		dma_unmap_single(dev, drv_data->rx_dma,
		drv_data->rx_map_len, DMA_FROM_DEVICE);
		dma_unmap_single(dev, drv_data->tx_dma,
		drv_data->tx_map_len, DMA_TO_DEVICE);
		}

		drv_data->dma_mapped = 0;
		}

		static int wait_ssp_rx_stall(void const __iomem *ioaddr)
		{
		unsigned long limit = loops_per_jiffy << 1;

		while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
		cpu_relax();

		return limit;
		}

		static int wait_dma_channel_stop(int channel)
		{
		unsigned long limit = loops_per_jiffy << 1;

		while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
		cpu_relax();

		return limit;
		}

		static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
		const char *msg)
		{
		void __iomem *reg = drv_data->ioaddr;

		/* Stop and reset */
		DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
		DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
		write_SSSR_CS(drv_data, drv_data->clear_sr);
		write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
		if (!pxa25x_ssp_comp(drv_data))
		write_SSTO(0, reg);
		pxa2xx_spi_flush(drv_data);
		write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);

		pxa2xx_spi_unmap_dma_buffers(drv_data);

		dev_err(&drv_data->pdev->dev, "%s\n", msg);

		drv_data->cur_msg->state = ERROR_STATE;
		tasklet_schedule(&drv_data->pump_transfers);
		}

		static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
		{
		void __iomem *reg = drv_data->ioaddr;
		struct spi_message *msg = drv_data->cur_msg;

		/* Clear and disable interrupts on SSP and DMA channels*/
		write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
		write_SSSR_CS(drv_data, drv_data->clear_sr);
		DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
		DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

		if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
		dev_err(&drv_data->pdev->dev,
		"dma_handler: dma rx channel stop failed\n");

		if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
		dev_err(&drv_data->pdev->dev,
		"dma_transfer: ssp rx stall failed\n");

		pxa2xx_spi_unmap_dma_buffers(drv_data);

		/* update the buffer pointer for the amount completed in dma */
		drv_data->rx += drv_data->len -
		(DCMD(drv_data->rx_channel) & DCMD_LENGTH);

		/* read trailing data from fifo, it does not matter how many
		* bytes are in the fifo just read until buffer is full
		* or fifo is empty, which ever occurs first */
		drv_data->read(drv_data);

		/* return count of what was actually read */
		msg->actual_length += drv_data->len -
		(drv_data->rx_end - drv_data->rx);

		/* Transfer delays and chip select release are
		* handled in pump_transfers or giveback
		*/

		/* Move to next transfer */
		msg->state = pxa2xx_spi_next_transfer(drv_data);

		/* Schedule transfer tasklet */
		tasklet_schedule(&drv_data->pump_transfers);
		}

		void pxa2xx_spi_dma_handler(int channel, void *data)
		{
		struct driver_data *drv_data = data;
		u32 irq_status = DCSR(channel) & DMA_INT_MASK;

		if (irq_status & DCSR_BUSERR) {

		if (channel == drv_data->tx_channel)
		pxa2xx_spi_dma_error_stop(drv_data,
		"dma_handler: bad bus address on tx channel");
		else
		pxa2xx_spi_dma_error_stop(drv_data,
		"dma_handler: bad bus address on rx channel");
		return;
		}

		/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
		if ((channel == drv_data->tx_channel)
		&& (irq_status & DCSR_ENDINTR)
		&& (drv_data->ssp_type == PXA25x_SSP)) {

		/* Wait for rx to stall */
		if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
		dev_err(&drv_data->pdev->dev,
		"dma_handler: ssp rx stall failed\n");

		/* finish this transfer, start the next */
		pxa2xx_spi_dma_transfer_complete(drv_data);
		}
		}

		irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
		{
		u32 irq_status;
		void __iomem *reg = drv_data->ioaddr;

		irq_status = read_SSSR(reg) & drv_data->mask_sr;
		if (irq_status & SSSR_ROR) {
		pxa2xx_spi_dma_error_stop(drv_data,
		"dma_transfer: fifo overrun");
		return IRQ_HANDLED;
		}

		/* Check for false positive timeout */
		if ((irq_status & SSSR_TINT)
		&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
		write_SSSR(SSSR_TINT, reg);
		return IRQ_HANDLED;
		}

		if (irq_status & SSSR_TINT \|\| drv_data->rx == drv_data->rx_end) {

		/* Clear and disable timeout interrupt, do the rest in
		* dma_transfer_complete */
		if (!pxa25x_ssp_comp(drv_data))
		write_SSTO(0, reg);

		/* finish this transfer, start the next */
		pxa2xx_spi_dma_transfer_complete(drv_data);

		return IRQ_HANDLED;
		}

		/* Opps problem detected */
		return IRQ_NONE;
		}

		int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
		{
		u32 dma_width;

		switch (drv_data->n_bytes) {
		case 1:
		dma_width = DCMD_WIDTH1;
		break;
		case 2:
		dma_width = DCMD_WIDTH2;
		break;
		default:
		dma_width = DCMD_WIDTH4;
		break;
		}

		/* Setup rx DMA Channel */
		DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
		DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
		DTADR(drv_data->rx_channel) = drv_data->rx_dma;
		if (drv_data->rx == drv_data->null_dma_buf)
		/* No target address increment */
		DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
		\| dma_width
		\| dma_burst
		\| drv_data->len;
		else
		DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
		\| DCMD_FLOWSRC
		\| dma_width
		\| dma_burst
		\| drv_data->len;

		/* Setup tx DMA Channel */
		DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
		DSADR(drv_data->tx_channel) = drv_data->tx_dma;
		DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
		if (drv_data->tx == drv_data->null_dma_buf)
		/* No source address increment */
		DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
		\| dma_width
		\| dma_burst
		\| drv_data->len;
		else
		DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
		\| DCMD_FLOWTRG
		\| dma_width
		\| dma_burst
		\| drv_data->len;

		/* Enable dma end irqs on SSP to detect end of transfer */
		if (drv_data->ssp_type == PXA25x_SSP)
		DCMD(drv_data->tx_channel) \|= DCMD_ENDIRQEN;

		return 0;
		}

		void pxa2xx_spi_dma_start(struct driver_data *drv_data)
		{
		DCSR(drv_data->rx_channel) \|= DCSR_RUN;
		DCSR(drv_data->tx_channel) \|= DCSR_RUN;
		}

		int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
		{
		struct device *dev = &drv_data->pdev->dev;
		struct ssp_device *ssp = drv_data->ssp;

		/* Get two DMA channels (rx and tx) */
		drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
		DMA_PRIO_HIGH,
		pxa2xx_spi_dma_handler,
		drv_data);
		if (drv_data->rx_channel < 0) {
		dev_err(dev, "problem (%d) requesting rx channel\n",
		drv_data->rx_channel);
		return -ENODEV;
		}
		drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
		DMA_PRIO_MEDIUM,
		pxa2xx_spi_dma_handler,
		drv_data);
		if (drv_data->tx_channel < 0) {
		dev_err(dev, "problem (%d) requesting tx channel\n",
		drv_data->tx_channel);
		pxa_free_dma(drv_data->rx_channel);
		return -ENODEV;
		}

		DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD \| drv_data->rx_channel;
		DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD \| drv_data->tx_channel;

		return 0;
		}

		void pxa2xx_spi_dma_release(struct driver_data *drv_data)
		{
		struct ssp_device *ssp = drv_data->ssp;

		DRCMR(ssp->drcmr_rx) = 0;
		DRCMR(ssp->drcmr_tx) = 0;

		if (drv_data->tx_channel != 0)
		pxa_free_dma(drv_data->tx_channel);
		if (drv_data->rx_channel != 0)
		pxa_free_dma(drv_data->rx_channel);
		}

		void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
		{
		if (drv_data->rx_channel != -1)
		DRCMR(drv_data->ssp->drcmr_rx) =
		DRCMR_MAPVLD \| drv_data->rx_channel;
		if (drv_data->tx_channel != -1)
		DRCMR(drv_data->ssp->drcmr_tx) =
		DRCMR_MAPVLD \| drv_data->tx_channel;
		}

		int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
		struct spi_device *spi,
		u8 bits_per_word, u32 *burst_code,
		u32 *threshold)
		{
		struct pxa2xx_spi_chip *chip_info =
		(struct pxa2xx_spi_chip *)spi->controller_data;
		int bytes_per_word;
		int burst_bytes;
		int thresh_words;
		int req_burst_size;
		int retval = 0;

		/* Set the threshold (in registers) to equal the same amount of data
		* as represented by burst size (in bytes). The computation below
		* is (burst_size rounded up to nearest 8 byte, word or long word)
		* divided by (bytes/register); the tx threshold is the inverse of
		* the rx, so that there will always be enough data in the rx fifo
		* to satisfy a burst, and there will always be enough space in the
		* tx fifo to accept a burst (a tx burst will overwrite the fifo if
		* there is not enough space), there must always remain enough empty
		* space in the rx fifo for any data loaded to the tx fifo.
		* Whenever burst_size (in bytes) equals bits/word, the fifo threshold
		* will be 8, or half the fifo;
		* The threshold can only be set to 2, 4 or 8, but not 16, because
		* to burst 16 to the tx fifo, the fifo would have to be empty;
		* however, the minimum fifo trigger level is 1, and the tx will
		* request service when the fifo is at this level, with only 15 spaces.
		*/

		/* find bytes/word */
		if (bits_per_word <= 8)
		bytes_per_word = 1;
		else if (bits_per_word <= 16)
		bytes_per_word = 2;
		else
		bytes_per_word = 4;

		/* use struct pxa2xx_spi_chip->dma_burst_size if available */
		if (chip_info)
		req_burst_size = chip_info->dma_burst_size;
		else {
		switch (chip->dma_burst_size) {
		default:
		/* if the default burst size is not set,
		* do it now */
		chip->dma_burst_size = DCMD_BURST8;
		case DCMD_BURST8:
		req_burst_size = 8;
		break;
		case DCMD_BURST16:
		req_burst_size = 16;
		break;
		case DCMD_BURST32:
		req_burst_size = 32;
		break;
		}
		}
		if (req_burst_size <= 8) {
		*burst_code = DCMD_BURST8;
		burst_bytes = 8;
		} else if (req_burst_size <= 16) {
		if (bytes_per_word == 1) {
		/* don't burst more than 1/2 the fifo */
		*burst_code = DCMD_BURST8;
		burst_bytes = 8;
		retval = 1;
		} else {
		*burst_code = DCMD_BURST16;
		burst_bytes = 16;
		}
		} else {
		if (bytes_per_word == 1) {
		/* don't burst more than 1/2 the fifo */
		*burst_code = DCMD_BURST8;
		burst_bytes = 8;
		retval = 1;
		} else if (bytes_per_word == 2) {
		/* don't burst more than 1/2 the fifo */
		*burst_code = DCMD_BURST16;
		burst_bytes = 16;
		retval = 1;
		} else {
		*burst_code = DCMD_BURST32;
		burst_bytes = 32;
		}
		}

		thresh_words = burst_bytes / bytes_per_word;

		/* thresh_words will be between 2 and 8 */
		*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
		\| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);

		return retval;
		}

drivers/spi/spi-pxa2xx.c

+332 −576

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