Merge "dt-bindings: clock: Remove qspi support for KONA" (0d3fafb2) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/debugcc-kona.c

+1 −7

Original line number	Original line	Diff line number	Diff line
	// SPDX-License-Identifier: GPL-2.0-only		// SPDX-License-Identifier: GPL-2.0-only
	/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */		/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */

	#define pr_fmt(fmt) "clk: %s: " fmt, __func__		#define pr_fmt(fmt) "clk: %s: " fmt, __func__

	@@ -191,8 +191,6 @@ static const char *const debug_mux_parent_names[] = {
	"gcc_qmip_disp_ahb_clk",		"gcc_qmip_disp_ahb_clk",
	"gcc_qmip_video_cvp_ahb_clk",		"gcc_qmip_video_cvp_ahb_clk",
	"gcc_qmip_video_vcodec_ahb_clk",		"gcc_qmip_video_vcodec_ahb_clk",
	"gcc_qspi_cnoc_periph_ahb_clk",
	"gcc_qspi_core_clk",
	"gcc_qupv3_wrap0_s0_clk",		"gcc_qupv3_wrap0_s0_clk",
	"gcc_qupv3_wrap0_s1_clk",		"gcc_qupv3_wrap0_s1_clk",
	"gcc_qupv3_wrap0_s2_clk",		"gcc_qupv3_wrap0_s2_clk",
	@@ -657,10 +655,6 @@ static struct clk_debug_mux gcc_debug_mux = {
	0x46, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },		0x46, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
	{ "gcc_qmip_video_vcodec_ahb_clk", 0x47, 1, GCC,		{ "gcc_qmip_video_vcodec_ahb_clk", 0x47, 1, GCC,
	0x47, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },		0x47, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
	{ "gcc_qspi_cnoc_periph_ahb_clk", 0x177, 1, GCC,
	0x177, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
	{ "gcc_qspi_core_clk", 0x178, 1, GCC,
	0x178, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
	{ "gcc_qupv3_wrap0_s0_clk", 0x89, 1, GCC,		{ "gcc_qupv3_wrap0_s0_clk", 0x89, 1, GCC,
	0x89, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },		0x89, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x62004, 0x62008 },
	{ "gcc_qupv3_wrap0_s1_clk", 0x8A, 1, GCC,		{ "gcc_qupv3_wrap0_s1_clk", 0x8A, 1, GCC,

drivers/clk/qcom/gcc-kona.c

+3 −68

Original line number	Original line	Diff line number	Diff line
	@@ -493,36 +493,6 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
	},		},
	};		};

	static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
	F(19200000, P_BI_TCXO, 1, 0, 0),
	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
	{ }
	};

	static struct clk_rcg2 gcc_qspi_core_clk_src = {
	.cmd_rcgr = 0x4b008,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = gcc_parent_map_0,
	.freq_tbl = ftbl_gcc_qspi_core_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "gcc_qspi_core_clk_src",
	.parent_names = gcc_parent_names_0,
	.num_parents = 4,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_rcg2_ops,
	.vdd_class = &vdd_cx,
	.num_rate_max = VDD_NUM,
	.rate_max = (unsigned long[VDD_NUM]) {
	[VDD_MIN] = 19200000,
	[VDD_LOWER] = 75000000,
	[VDD_LOW] = 150000000,
	[VDD_NOMINAL] = 300000000},
	},
	};

	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {		static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),		F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),		F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
	@@ -2226,7 +2196,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {

	static struct clk_branch gcc_pcie_0_pipe_clk = {		static struct clk_branch gcc_pcie_0_pipe_clk = {
	.halt_reg = 0x6b02c,		.halt_reg = 0x6b02c,
	.halt_check = BRANCH_HALT_DELAY,		.halt_check = BRANCH_HALT_SKIP,
	.clkr = {		.clkr = {
	.enable_reg = 0x52008,		.enable_reg = 0x52008,
	.enable_mask = BIT(4),		.enable_mask = BIT(4),
	@@ -2313,7 +2283,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {

	static struct clk_branch gcc_pcie_1_pipe_clk = {		static struct clk_branch gcc_pcie_1_pipe_clk = {
	.halt_reg = 0x8d02c,		.halt_reg = 0x8d02c,
	.halt_check = BRANCH_HALT_DELAY,		.halt_check = BRANCH_HALT_SKIP,
	.clkr = {		.clkr = {
	.enable_reg = 0x52000,		.enable_reg = 0x52000,
	.enable_mask = BIT(30),		.enable_mask = BIT(30),
	@@ -2400,7 +2370,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {

	static struct clk_branch gcc_pcie_2_pipe_clk = {		static struct clk_branch gcc_pcie_2_pipe_clk = {
	.halt_reg = 0x602c,		.halt_reg = 0x602c,
	.halt_check = BRANCH_HALT_DELAY,		.halt_check = BRANCH_HALT_SKIP,
	.clkr = {		.clkr = {
	.enable_reg = 0x52010,		.enable_reg = 0x52010,
	.enable_mask = BIT(15),		.enable_mask = BIT(15),
	@@ -2630,37 +2600,6 @@ static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
	},		},
	};		};

	static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
	.halt_reg = 0x4b000,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x4b000,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gcc_qspi_cnoc_periph_ahb_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gcc_qspi_core_clk = {
	.halt_reg = 0x4b004,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x4b004,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gcc_qspi_core_clk",
	.parent_names = (const char *[]){
	"gcc_qspi_core_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {		static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
	.halt_reg = 0x23008,		.halt_reg = 0x23008,
	.halt_check = BRANCH_HALT_VOTED,		.halt_check = BRANCH_HALT_VOTED,
	@@ -4137,9 +4076,6 @@ static struct clk_regmap *gcc_kona_clocks[] = {
	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,		[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,		[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,		[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,		[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,		[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,		[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
	@@ -4303,7 +4239,6 @@ static const struct qcom_reset_map gcc_kona_resets[] = {
	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },		[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
	[GCC_PDM_BCR] = { 0x33000 },		[GCC_PDM_BCR] = { 0x33000 },
	[GCC_PRNG_BCR] = { 0x34000 },		[GCC_PRNG_BCR] = { 0x34000 },
	[GCC_QSPI_BCR] = { 0x24008 },
	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },		[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },		[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },		[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },

include/dt-bindings/clock/qcom,gcc-kona.h

+145 −149

Original line number	Original line	Diff line number	Diff line
	@@ -100,133 +100,130 @@
	#define GCC_QMIP_DISP_AHB_CLK 88		#define GCC_QMIP_DISP_AHB_CLK 88
	#define GCC_QMIP_VIDEO_CVP_AHB_CLK 89		#define GCC_QMIP_VIDEO_CVP_AHB_CLK 89
	#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 90		#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 90
	#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 91		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 91
	#define GCC_QSPI_CORE_CLK 92		#define GCC_QUPV3_WRAP0_CORE_CLK 92
	#define GCC_QSPI_CORE_CLK_SRC 93		#define GCC_QUPV3_WRAP0_S0_CLK 93
	#define GCC_QUPV3_WRAP0_CORE_2X_CLK 94		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 94
	#define GCC_QUPV3_WRAP0_CORE_CLK 95		#define GCC_QUPV3_WRAP0_S1_CLK 95
	#define GCC_QUPV3_WRAP0_S0_CLK 96		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 96
	#define GCC_QUPV3_WRAP0_S0_CLK_SRC 97		#define GCC_QUPV3_WRAP0_S2_CLK 97
	#define GCC_QUPV3_WRAP0_S1_CLK 98		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 98
	#define GCC_QUPV3_WRAP0_S1_CLK_SRC 99		#define GCC_QUPV3_WRAP0_S3_CLK 99
	#define GCC_QUPV3_WRAP0_S2_CLK 100		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 100
	#define GCC_QUPV3_WRAP0_S2_CLK_SRC 101		#define GCC_QUPV3_WRAP0_S4_CLK 101
	#define GCC_QUPV3_WRAP0_S3_CLK 102		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 102
	#define GCC_QUPV3_WRAP0_S3_CLK_SRC 103		#define GCC_QUPV3_WRAP0_S5_CLK 103
	#define GCC_QUPV3_WRAP0_S4_CLK 104		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 104
	#define GCC_QUPV3_WRAP0_S4_CLK_SRC 105		#define GCC_QUPV3_WRAP0_S6_CLK 105
	#define GCC_QUPV3_WRAP0_S5_CLK 106		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 106
	#define GCC_QUPV3_WRAP0_S5_CLK_SRC 107		#define GCC_QUPV3_WRAP0_S7_CLK 107
	#define GCC_QUPV3_WRAP0_S6_CLK 108		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 108
	#define GCC_QUPV3_WRAP0_S6_CLK_SRC 109		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 109
	#define GCC_QUPV3_WRAP0_S7_CLK 110		#define GCC_QUPV3_WRAP1_CORE_CLK 110
	#define GCC_QUPV3_WRAP0_S7_CLK_SRC 111		#define GCC_QUPV3_WRAP1_S0_CLK 111
	#define GCC_QUPV3_WRAP1_CORE_2X_CLK 112		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 112
	#define GCC_QUPV3_WRAP1_CORE_CLK 113		#define GCC_QUPV3_WRAP1_S1_CLK 113
	#define GCC_QUPV3_WRAP1_S0_CLK 114		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 114
	#define GCC_QUPV3_WRAP1_S0_CLK_SRC 115		#define GCC_QUPV3_WRAP1_S2_CLK 115
	#define GCC_QUPV3_WRAP1_S1_CLK 116		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 116
	#define GCC_QUPV3_WRAP1_S1_CLK_SRC 117		#define GCC_QUPV3_WRAP1_S3_CLK 117
	#define GCC_QUPV3_WRAP1_S2_CLK 118		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 118
	#define GCC_QUPV3_WRAP1_S2_CLK_SRC 119		#define GCC_QUPV3_WRAP1_S4_CLK 119
	#define GCC_QUPV3_WRAP1_S3_CLK 120		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 120
	#define GCC_QUPV3_WRAP1_S3_CLK_SRC 121		#define GCC_QUPV3_WRAP1_S5_CLK 121
	#define GCC_QUPV3_WRAP1_S4_CLK 122		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 122
	#define GCC_QUPV3_WRAP1_S4_CLK_SRC 123		#define GCC_QUPV3_WRAP2_CORE_2X_CLK 123
	#define GCC_QUPV3_WRAP1_S5_CLK 124		#define GCC_QUPV3_WRAP2_CORE_CLK 124
	#define GCC_QUPV3_WRAP1_S5_CLK_SRC 125		#define GCC_QUPV3_WRAP2_S0_CLK 125
	#define GCC_QUPV3_WRAP2_CORE_2X_CLK 126		#define GCC_QUPV3_WRAP2_S0_CLK_SRC 126
	#define GCC_QUPV3_WRAP2_CORE_CLK 127		#define GCC_QUPV3_WRAP2_S1_CLK 127
	#define GCC_QUPV3_WRAP2_S0_CLK 128		#define GCC_QUPV3_WRAP2_S1_CLK_SRC 128
	#define GCC_QUPV3_WRAP2_S0_CLK_SRC 129		#define GCC_QUPV3_WRAP2_S2_CLK 129
	#define GCC_QUPV3_WRAP2_S1_CLK 130		#define GCC_QUPV3_WRAP2_S2_CLK_SRC 130
	#define GCC_QUPV3_WRAP2_S1_CLK_SRC 131		#define GCC_QUPV3_WRAP2_S3_CLK 131
	#define GCC_QUPV3_WRAP2_S2_CLK 132		#define GCC_QUPV3_WRAP2_S3_CLK_SRC 132
	#define GCC_QUPV3_WRAP2_S2_CLK_SRC 133		#define GCC_QUPV3_WRAP2_S4_CLK 133
	#define GCC_QUPV3_WRAP2_S3_CLK 134		#define GCC_QUPV3_WRAP2_S4_CLK_SRC 134
	#define GCC_QUPV3_WRAP2_S3_CLK_SRC 135		#define GCC_QUPV3_WRAP2_S5_CLK 135
	#define GCC_QUPV3_WRAP2_S4_CLK 136		#define GCC_QUPV3_WRAP2_S5_CLK_SRC 136
	#define GCC_QUPV3_WRAP2_S4_CLK_SRC 137		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 137
	#define GCC_QUPV3_WRAP2_S5_CLK 138		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 138
	#define GCC_QUPV3_WRAP2_S5_CLK_SRC 139		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 139
	#define GCC_QUPV3_WRAP_0_M_AHB_CLK 140		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 140
	#define GCC_QUPV3_WRAP_0_S_AHB_CLK 141		#define GCC_QUPV3_WRAP_2_M_AHB_CLK 141
	#define GCC_QUPV3_WRAP_1_M_AHB_CLK 142		#define GCC_QUPV3_WRAP_2_S_AHB_CLK 142
	#define GCC_QUPV3_WRAP_1_S_AHB_CLK 143		#define GCC_SDCC2_AHB_CLK 143
	#define GCC_QUPV3_WRAP_2_M_AHB_CLK 144		#define GCC_SDCC2_APPS_CLK 144
	#define GCC_QUPV3_WRAP_2_S_AHB_CLK 145		#define GCC_SDCC2_APPS_CLK_SRC 145
	#define GCC_SDCC2_AHB_CLK 146		#define GCC_SDCC4_AHB_CLK 146
	#define GCC_SDCC2_APPS_CLK 147		#define GCC_SDCC4_APPS_CLK 147
	#define GCC_SDCC2_APPS_CLK_SRC 148		#define GCC_SDCC4_APPS_CLK_SRC 148
	#define GCC_SDCC4_AHB_CLK 149		#define GCC_SYS_NOC_CPUSS_AHB_CLK 149
	#define GCC_SDCC4_APPS_CLK 150		#define GCC_TSIF_AHB_CLK 150
	#define GCC_SDCC4_APPS_CLK_SRC 151		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 151
	#define GCC_SYS_NOC_CPUSS_AHB_CLK 152		#define GCC_TSIF_REF_CLK 152
	#define GCC_TSIF_AHB_CLK 153		#define GCC_TSIF_REF_CLK_SRC 153
	#define GCC_TSIF_INACTIVITY_TIMERS_CLK 154		#define GCC_UFS_1X_CLKREF_EN 154
	#define GCC_TSIF_REF_CLK 155		#define GCC_UFS_CARD_AHB_CLK 155
	#define GCC_TSIF_REF_CLK_SRC 156		#define GCC_UFS_CARD_AXI_CLK 156
	#define GCC_UFS_1X_CLKREF_EN 157		#define GCC_UFS_CARD_AXI_CLK_SRC 157
	#define GCC_UFS_CARD_AHB_CLK 158		#define GCC_UFS_CARD_AXI_HW_CTL_CLK 158
	#define GCC_UFS_CARD_AXI_CLK 159		#define GCC_UFS_CARD_ICE_CORE_CLK 159
	#define GCC_UFS_CARD_AXI_CLK_SRC 160		#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 160
	#define GCC_UFS_CARD_AXI_HW_CTL_CLK 161		#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 161
	#define GCC_UFS_CARD_ICE_CORE_CLK 162		#define GCC_UFS_CARD_PHY_AUX_CLK 162
	#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 163		#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 163
	#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 164		#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 164
	#define GCC_UFS_CARD_PHY_AUX_CLK 165		#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 165
	#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 166		#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 166
	#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 167		#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 167
	#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 168		#define GCC_UFS_CARD_UNIPRO_CORE_CLK 168
	#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 169		#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 169
	#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 170		#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 170
	#define GCC_UFS_CARD_UNIPRO_CORE_CLK 171		#define GCC_UFS_PHY_AHB_CLK 171
	#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 172		#define GCC_UFS_PHY_AXI_CLK 172
	#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 173		#define GCC_UFS_PHY_AXI_CLK_SRC 173
	#define GCC_UFS_PHY_AHB_CLK 174		#define GCC_UFS_PHY_AXI_HW_CTL_CLK 174
	#define GCC_UFS_PHY_AXI_CLK 175		#define GCC_UFS_PHY_ICE_CORE_CLK 175
	#define GCC_UFS_PHY_AXI_CLK_SRC 176		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 176
	#define GCC_UFS_PHY_AXI_HW_CTL_CLK 177		#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 177
	#define GCC_UFS_PHY_ICE_CORE_CLK 178		#define GCC_UFS_PHY_PHY_AUX_CLK 178
	#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 179		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 179
	#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 180		#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 180
	#define GCC_UFS_PHY_PHY_AUX_CLK 181		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181
	#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 182		#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 182
	#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 183		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 183
	#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 184		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 184
	#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 185		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 185
	#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 186		#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 186
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK 187		#define GCC_USB30_PRIM_MASTER_CLK 187
	#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 188		#define GCC_USB30_PRIM_MASTER_CLK_SRC 188
	#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 189		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 189
	#define GCC_USB30_PRIM_MASTER_CLK 190		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 190
	#define GCC_USB30_PRIM_MASTER_CLK_SRC 191		#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 191
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK 192		#define GCC_USB30_PRIM_SLEEP_CLK 192
	#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 193		#define GCC_USB30_SEC_MASTER_CLK 193
	#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 194		#define GCC_USB30_SEC_MASTER_CLK_SRC 194
	#define GCC_USB30_PRIM_SLEEP_CLK 195		#define GCC_USB30_SEC_MOCK_UTMI_CLK 195
	#define GCC_USB30_SEC_MASTER_CLK 196		#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 196
	#define GCC_USB30_SEC_MASTER_CLK_SRC 197		#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 197
	#define GCC_USB30_SEC_MOCK_UTMI_CLK 198		#define GCC_USB30_SEC_SLEEP_CLK 198
	#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 199		#define GCC_USB3_PRIM_PHY_AUX_CLK 199
	#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 200		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 200
	#define GCC_USB30_SEC_SLEEP_CLK 201		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 201
	#define GCC_USB3_PRIM_PHY_AUX_CLK 202		#define GCC_USB3_PRIM_PHY_PIPE_CLK 202
	#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 203		#define GCC_USB3_SEC_CLKREF_EN 203
	#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 204		#define GCC_USB3_SEC_PHY_AUX_CLK 204
	#define GCC_USB3_PRIM_PHY_PIPE_CLK 205		#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 205
	#define GCC_USB3_SEC_CLKREF_EN 206		#define GCC_USB3_SEC_PHY_COM_AUX_CLK 206
	#define GCC_USB3_SEC_PHY_AUX_CLK 207		#define GCC_USB3_SEC_PHY_PIPE_CLK 207
	#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 208		#define GCC_VIDEO_AHB_CLK 208
	#define GCC_USB3_SEC_PHY_COM_AUX_CLK 209		#define GCC_VIDEO_AXI0_CLK 209
	#define GCC_USB3_SEC_PHY_PIPE_CLK 210		#define GCC_VIDEO_AXI1_CLK 210
	#define GCC_VIDEO_AHB_CLK 211		#define GCC_VIDEO_XO_CLK 211
	#define GCC_VIDEO_AXI0_CLK 212		#define GPLL0 212
	#define GCC_VIDEO_AXI1_CLK 213		#define GPLL0_OUT_EVEN 213
	#define GCC_VIDEO_XO_CLK 214		#define GPLL9 214
	#define GPLL0 215
	#define GPLL0_OUT_EVEN 216
	#define GPLL9 217

	/* GCC resets */		/* GCC resets */
	#define GCC_DPM_BCR 0		#define GCC_DPM_BCR 0
	@@ -254,27 +251,26 @@
	#define GCC_PCIE_PHY_COM_BCR 22		#define GCC_PCIE_PHY_COM_BCR 22
	#define GCC_PDM_BCR 23		#define GCC_PDM_BCR 23
	#define GCC_PRNG_BCR 24		#define GCC_PRNG_BCR 24
	#define GCC_QSPI_BCR 25		#define GCC_QUPV3_WRAPPER_0_BCR 25
	#define GCC_QUPV3_WRAPPER_0_BCR 26		#define GCC_QUPV3_WRAPPER_1_BCR 26
	#define GCC_QUPV3_WRAPPER_1_BCR 27		#define GCC_QUPV3_WRAPPER_2_BCR 27
	#define GCC_QUPV3_WRAPPER_2_BCR 28		#define GCC_QUSB2PHY_PRIM_BCR 28
	#define GCC_QUSB2PHY_PRIM_BCR 29		#define GCC_QUSB2PHY_SEC_BCR 29
	#define GCC_QUSB2PHY_SEC_BCR 30		#define GCC_SDCC2_BCR 30
	#define GCC_SDCC2_BCR 31		#define GCC_SDCC4_BCR 31
	#define GCC_SDCC4_BCR 32		#define GCC_TSIF_BCR 32
	#define GCC_TSIF_BCR 33		#define GCC_UFS_CARD_BCR 33
	#define GCC_UFS_CARD_BCR 34		#define GCC_UFS_PHY_BCR 34
	#define GCC_UFS_PHY_BCR 35		#define GCC_USB30_PRIM_BCR 35
	#define GCC_USB30_PRIM_BCR 36		#define GCC_USB30_SEC_BCR 36
	#define GCC_USB30_SEC_BCR 37		#define GCC_USB3_DP_PHY_PRIM_BCR 37
	#define GCC_USB3_DP_PHY_PRIM_BCR 38		#define GCC_USB3_DP_PHY_SEC_BCR 38
	#define GCC_USB3_DP_PHY_SEC_BCR 39		#define GCC_USB3_PHY_PRIM_BCR 39
	#define GCC_USB3_PHY_PRIM_BCR 40		#define GCC_USB3_PHY_SEC_BCR 40
	#define GCC_USB3_PHY_SEC_BCR 41		#define GCC_USB3PHY_PHY_PRIM_BCR 41
	#define GCC_USB3PHY_PHY_PRIM_BCR 42		#define GCC_USB3PHY_PHY_SEC_BCR 42
	#define GCC_USB3PHY_PHY_SEC_BCR 43		#define GCC_USB_PHY_CFG_AHB2PHY_BCR 43
	#define GCC_USB_PHY_CFG_AHB2PHY_BCR 44		#define GCC_VIDEO_AXI0_CLK_ARES 44
	#define GCC_VIDEO_AXI0_CLK_ARES 45		#define GCC_VIDEO_AXI1_CLK_ARES 45
	#define GCC_VIDEO_AXI1_CLK_ARES 46

	#endif		#endif